Datasheet

EN1

Vo1

Vo2

t - Time = 1 ms/div

SS/TR1

TPS54478

EN1

PWRGD1

SS/TR2

TPS54478

EN2

PWRGD2

Vout2 Vssoffset

R1 =

Vref Iss

Vref R1

R2 =

Vout2 Vref

TPS54478

SLVSAS2 – JUNE 2011

www.ti.com

Figure 25. Schematic for Ratio-metric Start-Up Figure 26. Ratio-metric Startup

Sequence

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Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2

shown in Figure 27 to the output of the power supply that needs to be tracked or another voltage reference

source. Using Equation 5 and Equation 6, the tracking resistors can be calculated. To minimize the effect of the

inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current

source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. As the

SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the

slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin

voltage needs to be greater than 0.86 V for a complete handoff to the internal voltage reference as shown in

Figure 28.

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(5)

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(6)

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