Datasheet

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VIN

POWERPAD

BOOT

VSENSE

COMP

TPS54478

RT /CLK

SS/TR

PWRGD

BOOT

VOUT

VIN

AGND

GND

0 0.5 1 1.5 2 2.5 3 3.5 4

I - Output Current - A

V = 5 V

V = 3.3 V

F = 1 MHz,

DCR = 6.8 m ,

V = 1.8 V

Efficiency - %

TPS54478

www.ti.com

SLVSAS2 –JUNE 2011

2.95-V to 6-V Input, 4-A Output, 2-MHz, Synchronous Step-Down

Switcher With Integrated FETs ( SWIFT™)

Check for Samples: TPS54478

FEATURES

DESCRIPTION

The TPS54478 device is a full featured 6 V, 4 A,

• Two 30-mΩ (typical) MOSFETs for High

synchronous step down current mode converter with

Efficiency at 4 A Loads

two integrated MOSFETs.

• 200kHz to 2MHz Switching Frequency

The TPS54478 enables small designs by integrating

• 0.6 V ± 1% Voltage Reference Over

the MOSFETs, implementing current mode control to

Temperature (–40°C to 150°C)

reduce external component count, reducing inductor

• Start up with Pre-Biased Voltage

size by enabling up to 2 MHz switching frequency,

• Synchronizes to External Clock

and minimizing the IC footprint with a small 3mm x

• Adjustable Slow Start / Sequencing

3mm thermally enhanced QFN package.

• UV and OV Power Good Output

The TPS54478 provides accurate regulation for a

• Cycle by Cycle Current Limit and Hiccup

variety of loads with an accurate ±1% Voltage

Current Protection

Reference (VREF) over temperature.

• Thermally Enhanced 3mm × 3mm 16-pin QFN

Efficiency is maximized through the integrated 30mΩ

(RTE)

MOSFETs and 525μA typical supply current. Using

• Pin Compatible to TPS54418

the enable pin, shutdown supply current is reduced to

2.5µA by entering a shutdown mode.

APPLICATIONS

Under voltage lockout is internally set at 2.6 V, but

• Low-Voltage, High-Density Power Systems

can be increased by programming the threshold with

• Point of Load Regulation for High Performance

a resistor network on the enable pin. The output

DSPs, FPGAs, ASICs and Microprocessors

voltage startup ramp is controlled by the slow start

• Broadband, Networking and Optical

pin. An open drain power good signal indicates the

Communications Infrastructure

output is within 93% to 107% of its nominal voltage.

Cycle-by-cycle current limit, hiccup overcuurent

SIMPLIFIED SCHEMATIC

protection and thermal shutdown protect the device

during an overcurrent condition.

vertical spacer

The TPS54478 is supported in the SwitcherPro™

vertical spacer

Software Tool at www.ti.com/switcherpro.

For more SWIFT

documentation, see the TI

website at www.ti.com/swift.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT, SwitcherPro are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com 2.95-V to 6-V Input, 4-A Output, 2-MHz, Synchronous Step-Down Switcher With Integrated FETs ( SWIFT™) Check for Samples: TPS54478 FEATURES DESCRIPTION • The TPS54478 device is a full featured 6 V, 4 A, synchronous step down current mode converter with two integrated MOSFETs. 1 2 • • • • • • • • • Two 30-mΩ (typical) MOSFETs for High Efficiency at 4 A Loads 200kHz to 2MHz Switching Frequency 0.
PAGE 2
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) TJ PACKAGE PART NUMBER –40°C to 150°C 3 × 3 mm QFN TPS54478RTE For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.
PAGE 3
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com THERMAL INFORMATION TPS54478 THERMAL METRIC (1) (2) (3) (RTE) UNITS (QFN-16) PINS θJA Junction-to-ambient thermal resistance ψJT Junction-to-top characterization parameter 0.7 ψJB Junction-to-board characterization parameter 21.8 θJC(top) Junction-to-case(top) thermal resistance 50.7 θJC(bottom) Junction-to-case(bottom) thermal resistance 7.5 θJB Junction-to-board thermal resistance 21.8 (1) (2) (3) 49.
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TPS54478 SLVSAS2 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX 6.5 8.2 UNIT CURRENT LIMIT Current limit threshold VIN = 6V, Fs = 500 KHz 5.2 Cycles before entering hiccup Cycles of converter in off state during hiccup Low side Fet reverse current limit A 512 Cycles 16384 Cycles 3.
PAGE 5
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT Output low I(PWRGD) = 3 mA 0.2 0.3 V Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 1.2 1.
PAGE 6
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com PIN FUNCTIONS (continued) PIN NAME VSENSE DESCRIPTION NO. 6 Inverting node of the transconductance (gm) error amplifier.
PAGE 7
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS CURVES SHUTDOWN SUPPLY CURRENT vs TEMPERATURE VIN SUPPLY CURRENT vs TEMPERATURE 580 3 560 VIN = 5 V Ivin - Supply Current - mA Iq - Shutdown Supply Current - mA 570 2.5 2 VIN = 5 V 1.5 VIN = 3.3 V 1 550 540 530 VIN = 3.3 V 520 510 500 0.5 490 0 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 480 -50 150 -25 0 Figure 1. 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 2.
PAGE 8
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) HIGH SIDE FET CURRENT LIMIT vs TEMPERATURE TRANSCONDUCTANCE vs TEMPERATURE 7 HSFET Lim-High Side Fet Current Limit Current - A 310 EA - Transconductance - mA/V 290 270 VIN = 3.3 V 250 230 VIN = 5 V 210 190 170 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 VIN = 5 V 6.5 VIN = 3.3 V 6 5.5 5 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 7. 150 Figure 8.
PAGE 9
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) SS CHARGE CURRENT vs TEMPERATURE PWRGD Rdson vs TEMPERATURE 100 -2 -2.1 Vin = 5 V; Vss = 0.4 V 90 RDSON - Power Good - W ISS2 - SS Charge Current - mA -2.2 -2.3 Vin = 3.3 V; Vss = 0.4 V -2.4 -2.5 -2.6 -2.7 -2.8 80 70 VIN = 5 V 60 50 -2.9 -3 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 40 -50 150 -25 0 Figure 13. 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 14.
PAGE 10
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 100 100 95 95 90 90 VO = 2.5 V VO = 1.8 V VO = 1.2 V VO = 1 V 80 75 70 80 VO = 1.8 V VO = 1.2 V VO = 1 V 75 70 65 65 Vin = 3.3 V, DCR = 18 mW, Fs = 500 kHz, Tj = 25°C 60 55 50 VO = 3.3 V VO = 2.5 V 85 Efficiency - % Efficiency - % 85 0 0.5 1 1.5 2 2.5 IO - Output Current - A 3 3.5 Vin = 5 V, DCR = 18 mW, Fs = 500 kHz, Tj = 25°C 60 55 4 50 0 0.
PAGE 11
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com To reduce the power dissipation of TPS54478 during overcurrent event, the hiccup protection is implemented beyond the cycle-by-cycle protection. Thermal shutdown prevents the overheat damage of the device. DETAILED DESCRIPTION FIXED FREQUENCY PWM CONTROL The TPS54478 uses an adjustable fixed frequency, peak current mode control.
PAGE 12
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com TPS54478 VO R1 VSENSE – R2 0.6 V + Figure 21. Voltage Divider Circuit ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT The TPS54478 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher under-voltage lockout (UVLO), use the EN pin as shown in Figure 22 to adjust the input voltage UVLO by using two external resistors. It is recommended to use the EN resistors to set the UVLO falling threshold (VSTOP) above 2.6V.
PAGE 13
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com SLOW START / TRACKING PIN The TPS54478 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the SS/TR pin to ground implements a slow start time. Before the SS pin reaches the voltage threshold VSSTHR, the charge current is about 45 μA. The TPS54478 internal pull-up current source of 2.2 μA charges the external slow start capacitor after the SS pin voltage exceeds VSSTHR.
PAGE 14
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com TPS54478 EN1 EN1 SS/TR1 Io Vo1 PWRGD1 Vo2 TPS54478 EN2 SS/TR2 t - Time = 1 ms/div PWRGD2 Figure 25. Schematic for Ratio-metric Start-Up Sequence vertical spacer Figure 26. Ratio-metric Startup Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 27 to the output of the power supply that needs to be tracked or another voltage reference source.
PAGE 15
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com TPS54478 EN1 VOUT1 SS/TR1 PWRGD1 TPS54478 EN2 VOUT 2 EN1 = 5 / div SS2 = 500 mV / div Vo1 = 500 mV / div Vo2 = 500 mV / div R1 SS/TR2 R2 PWRGD2 Time = 1 msec / div Figure 27. Simultaneous Startup Sequence Figure 28.
PAGE 16
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com START-UP into Pre-Biased Output The TPS54478 features monotonic startup into pre-biased output. The low side Fet turns on for a very short time period every cycle before the output voltage reaches the pre-biased voltage. This ensures the boot cap has enough charge to turn on the top Fet when the output voltage reaches the pre-biased voltage. The TPS54478 also implements low side current protection by detecting the voltage over the low side MOSFET.
PAGE 17
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com POWER GOOD (PWRGD PIN) The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters the fault condition by falling below 93% or rising above 107% of the nominal internal reference voltage. There is a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 95% or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off.
PAGE 18
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL Figure 31 is a simple small signal model that can be used to understand how to design the frequency compensation without slope compensation effect. The TPS54478 power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor.
PAGE 19
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com VO R1 VSENSE COMP gmea R2 Vref RO CO 5pF Type 2A R3 C2 Type 2B R3 C1 C1 Figure 33. Type-II of Frequency Compensation The design guidelines for TPS54478 loop compensation will be addressed in the APPLICATION INFORMATION section with more details. The approach is to run the Pspice model first to find the accurate response of the power stage with slope compensation effect. The compensation network is then designed based on the desired crossover frequency.
PAGE 20
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com Vo C3 R1 VSENSE gm ea R2 Vref RO COMP CO Type 3 A R3 Type 3 B R3 C2 5 pF C1 C1 Figure 34.
PAGE 21
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com APPLICATION INFORMATION DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the TPS54478EVM-037 (PWR037) evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level.
PAGE 22
VIN 0.1 mF 220 pF C3 C2 C1 10 mF VIN= 3-6 V 1 C4 11.5 kW R2 14.3 kW R1 820 pF C5 30.9 kW R3 35.7 kW R4 C6 0.01 mF VSNS 8 RT/CLK 9 SS/TR 6 VSNS 7 COMP 2 VIN 15 EN 16 VIN 1 VIN U1 PH PH PH 17 PWPD AGND GND GND PWRGD BOOT TPS54478 5 4 3 14 13 12 11 10 1 100 kW R5 0.1 mF C7 1 VIN 2 Optional L1 1.2 mH 47 mF C8 47 mF C9 10 kW R7 20 kW R6 VOUT = 1.8 V, 4 A 220 pF C10 VSNS VOUT TPS54478 SLVSAS2 – JUNE 2011 www.ti.com Figure 35.
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TPS54478 SLVSAS2 – JUNE 2011 www.ti.com OUTPUT INDUCTOR SELECTION The inductor selected works for the entire TPS54478 input voltage range. To calculate the value of the output inductor, use Equation 19. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor.
PAGE 24
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com For this example, the transient load response is specified as a 3% change in Vout for a load step from 1 A (25% load) to 3 A (75% load). For this example, ΔIout = 3 - 1 = 2.0A and ΔVout= 0.03 × 1.8 = 0.054 V. Using these numbers gives a minimum capacitance of 74.1 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.
PAGE 25
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 28.
PAGE 26
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com æ Offtimemax ö æ tdead ö Voutmax = Vin ´ ç 1 ÷ - Ioutmax ´ (RDSmax + RI) - (0.
PAGE 27
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com 10 R3 = -GPWRSTG 20 gmEA × Vout VREF (34) To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 70 kHz. The required value for C5 is given by Equation 35. 1 C5 = F 2 × p × R3 × CO 10 (35) To maximize phase gain the high frequency pole is not implemented and C4 is not populated. The pole can be useful to offset the ESR of aluminum electrolytic output capacitors.
PAGE 28
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com VOUT = 50 mV / div (ac coupled) VIN = 5 V/div EN = 5 V/div VOUT = 2 V/div IOUT = 1 A / div Load step = 1 - 3 A, slew rate = 0.167 A / ms PWRGD = 5 V/div Time = 100 ms/div Time = 2 ms/div Figure 39. TRANSIENT RESPONSE, 2 A STEP Figure 40. POWER UP VOUT, VIN VIN = 5 V/div EN = 5 V/div EN = 5 V/div VOUT = 2 V/div VOUT = 500 mV/div PWRGD = 5 V/div Pre-bias voltage = 500 mV Time = 2 ms/div Figure 41. POWER UP VOUT, EN Time = 2 msec / div Figure 42.
PAGE 29
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com VIN = 100 mV/div (ac coupled) VOUT = 20 mV/div (ac coupled) PH = 2 V/div PH = 2 V/div Time = 500 ns/div Time = 500 ns/div Figure 45. OUTPUT RIPPLE, IOUT = 4 A Figure 46. INPUT RIPPLE, IOUT = 4 A 60 180 50 150 40 120 0.2 0.15 Gain - dB 20 60 Gain 10 30 0 0 -10 -30 -20 -60 -30 -90 -40 -120 -50 -150 Phase - Degrees 90 Output Voltage Deviation - % VIN = 5 V Phase 30 0.1 0.05 VIN = 3.3 V 0 -0.05 -0.1 -0.
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TPS54478 SLVSAS2 – JUNE 2011 www.ti.com VOUT = 1 V/div VOUT = 500 mV/div IOUT = 5 A/div Time = 5 ms/div Figure 51. HICCUP MODE CURRENT LIMIT Time = 500 ms/div Figure 52. START UP CHARACTERISTIC POWER DISSIPATION ESTIMATE The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation.
PAGE 31
TPS54478 www.ti.com SLVSAS2 – JUNE 2011 So Ptot = Pcon + Pd + Psw + Pgd + Pq For given TA, TJ = TA + Rth × Ptot For given TJMAX = 150°C TAmax = TJ max – Rth × Ptot Where: Ptot is the total device power dissipation (W). TA is the ambient temperature (°C). TJ is the junction temperature (°C). Rth is the thermal resistance of the package (°C/W). TJMAX is maximum junction temperature (°C). TAMAX is maximum ambient temperature (°C).
PAGE 32
TPS54478 SLVSAS2 – JUNE 2011 www.ti.com VIA to Ground Plane UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR BOOT PWRGD EN VIN VIN BOOT CAPACITOR VIN OUTPUT INDUCTOR PH VIN PH EXPOSED POWERPAD AREA GND PH GND VOUT OUTPUT FILTER CAPACITOR PH SLOW START CAPACITOR RT/CLK COMP VSENSE AGND SS FEEDBACK RESISTORS ANALOG GROUND TRACE FREQUENCY SET RESISTOR TOPSIDE GROUND AREA COMPENSATION NETWORK VIA to Ground Plane Figure 53.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 34
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54478RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54478RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
PAGE 35
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54478RTER WQFN RTE 16 3000 367.0 367.0 35.0 TPS54478RTET WQFN RTE 16 250 210.0 185.0 35.
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