Datasheet

V = 5 V / div

EN = 10 V / div

V = 1 V / div

OUT

Time = 2 msec / div

Board Layout

www.ti.com

The TPS54429EVM-608 start-up waveform relative to enable (EN) is shown in Figure 9.

Figure 9. TPS54429EVM-608 Start-Up Relative to EN

5 Board Layout

This section provides description of the TPS54429EVM-608, board layout, and layer illustrations.

5.1 Layout

The board layout for the TPS54429EVM-608 is shown in Figure 10 through Figure 15. The top layer

contains the main power traces for VIN, VO, and ground. Also on the top layer are connections for the

pins of the TPS54429 and a large area filled with ground. Most of the signal traces also are located on the

top side. The input decoupling capacitors are located as close to the IC as possible. The input and output

connectors, test points, and most of the components are located on the top side. R4, the power-good

pullup, is located on the back side. Analog ground and power ground are connected at a single point on

the top layer near pin 5 of the TPS54429. The internal layer 1 is a split plane containing analog and power

grounds. The internal layer 2 is primarily power ground but also has a fill area of VIN and a trace routing

VIN to the enable control jumper JP1. The bottom layer is primarily analog ground but also has traces to

connect VIN, traces for the power-good signal, and the feedback trace from VOUT to the voltage setpoint

divider network.

TPS54429EVM-608, 4.5-A, SWIFT™ Regulator— Evaluation Module SLVU443–March 2011

Submit Documentation Feedback