Datasheet

´Ro Co
C3 =
R3
gm
2 × c Vo Co
R3 =
Gm Vref VI
p ¦ ´ ´
´ ´
¦
¦ ¦ ´
C
sw
= p mod
2
¦ ¦ ´ ¦
C
= p mod z mod
¦
p ´ ´
1
z m od =
2 Resr Cout
¦
p ´ ´
Iout max
p m od =
2 Vout Cout
( )
( )
( )
( )
( )
( )
Voutmax 1 Offtimemax Fsmax Vinmin Ioutmax 2 RDS Ioutmax RL RDS= - ´ ´ - ´ ´ - ´ +
TPS54418
SLVS946C –MAY 2009–REVISED JULY 2013 www.ti.com
RDS = minimum high side MOSFET on resistance (30 - 44 mΩ)
RL = series resistance of output inductor (32)
There is also a maximum acheivable output voltage which is limited by the minimum off time. The maximum
output voltage is given by Equation 33
Where:
Voutmax = maximum achieveable output voltage
Offtimeman = maximum off time (60 nsec typical)
Fsmax = maximum switching frequency including tolerance
Vinmin = minimum input voltage
Ioutmax = maximum load current
RDS = maximum high side MOSFET on resistance (60 - 70 mΩ)
RL = series resistance of output inductor (33)
COMPENSATION
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54418. Since the slope compensation is ignored, the actual cross over frequency is usually lower than
the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 34 and
Equation 12. For Cout, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V
capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer
information to derate the capacitor value. Use Equation 36 and Equation 37 to estimate a starting point for the
crossover frequency, fc. For the example design, fpmod is 8.04 kHz and fzmod is 2412 kHz. Equation 36 is the
geometric mean of the modulator pole and the esr zero and Equation 37 is the mean of modulator pole and the
switching frequency. Equation 36 yields 139 kHz and Equation 37 gives 63 kHz. Use the lower value of
Equation 36 or Equation 37 as the maximum crossover frequency. For this example, fc is 35 kHz. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole (if needed).
(34)
(35)
(36)
(37)
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. Use Equation 38 to calculate the compensation network’s
resistor value. In this example, the anticipated cross-over frequency (fc) is 35 kHz. The power stage gain
(gm
ps
) is 13 A/V and the error amplifier gain (gm
ea
) is 225 μA/V.
(38)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation
network’s capacitor can be calculated from Equation 39.
(39)
3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to
add it.
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