Datasheet

TPS54418
SLVS946C –MAY 2009–REVISED JULY 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
J
PACKAGE PART NUMBER
–40°C to 150°C 3 × 3 mm QFN TPS54418RTE
ABSOLUTE MAXIMUM RATINGS
VALUE UNIT
Input voltage VIN –0.3 to 7 V
EN –0.3 to 7
BOOT PH + 8
VSENSE –0.3 to 3
COMP –0.3 to 3
PWRGD –0.3 to 7pau
SS –0.3 to 3
RT/CLK –0.3 to 6
Output voltage BOOT-PH 8 V
PH –0.6 to 7
PH 10 ns Transient –2 to 7
Source current EN 100 μA
RT/CLK 100 μA
Sink current COMP 100 μA
PWRGD 10 mA
SS 100 μA
Electrostatic discharge (HBM) 2 kV
Electrostatic discharge (CDM) 500 V
Operating Junction temperature, T
j
–40 to 150 °C
Storage temperature, T
stg
–65 to 150 °C
PACKAGE DISSIPATION RATINGS
(1) (2) (3)
over operating free-air temperature range (unless otherwise noted)
THERMAL IMPEDANCE φ
JT
THERMAL CHARACTERISTIC
PACKAGE
JUNCTION TO AMBIENT JUNCTION TO TOP
RTE 37°C/W 1°C/W
(1) Maximum power dissipation may be limited by overcurrent protection
(2) Power rating at a specific ambient temperature T
A
should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
information.
(3) Test boards conditions:
(a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 4 thermal vias (10mil) located under the device package
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