Datasheet

ps L
Adc = gm R´
s
1+
2 × z
vo
= Adc
vc
s
1+
2 × p
æ ö
ç ÷
p ¦
è ø
´
æ ö
ç ÷
p ¦
è ø
VO
R
L
VC
fp
fz
Adc
gm
ps
R
ESR
C
OUT
VSENSE
COMP
VO
R1
R3
C1
C2
R2
CO RO
gm
225 uA/V
0.8 V
PowerStage
13.0 A/V
PH
R
ESR
C
OUT
R
L
b
a
c
TPS54418
SLVS946C –MAY 2009–REVISED JULY 2013 www.ti.com
Figure 31. Small Signal Model for Loop Response
SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL
Figure 31 is a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54418 power stage can be approximated to a voltage controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 7 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of
the change in switch current and the change in COMP pin voltage (node c in Figure 31) is the power stage
transconductance. The gm for the TPS54418 is 13.0 A/V. The low frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 8. As the load
current increases and decreases, the low frequency gain decreases and increases, respectively. This variation
with load may seem problematic at first glance, but the dominant pole moves with load current [see Equation 9].
The combined effect is highlighted by the dashed line in the right half of Figure 32. As the load current
decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same
for the varying load conditions which makes it easier to design the frequency compensation.
Figure 32. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
(7)
(8)
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