Datasheet

SYNCClock=2V/div

PH=2V/div

Time=500nsec/div

TPS54418

Clock

Source

PLL

RT/CLK

TPS54418

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SLVS946C –MAY 2009–REVISED JULY 2013

Figure 29. Synchronizing to a System Clock Figure 30. Plot of Synchronizing to System Clock

POWER GOOD (PWRGD PIN)

The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters

the fault condition by falling below 91% or rising above 107% of the nominal internal reference voltage. There is

a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93%

or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off. It is

recommended to use a pull-up resistor between the values of 1kΩ and 100kΩ to a voltage source that is 6 V or

less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.2 V.

OVERVOLTAGE TRANSIENT PROTECTION

The TPS54418 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot

when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output

overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 109%

of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side

MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the

VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next

clock cycle.

THERMAL SHUTDOWN

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C.

The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal

trip threshold. Once the die temperature decreases below 160°C, the device reinitiates the power up sequence

by discharging the SS pin to 0 volts. The thermal shutdown hysteresis is 15°C.

SMALL SIGNAL MODEL FOR LOOP RESPONSE

Figure 31 shows an equivalent model for the TPS54418 control loop which can be modeled in a circuit simulation

program to check frequency response and dynamic load response. The error amplifier is a transconductance

amplifier with a gm of 225 μA/V. The error amplifier can be modeled using an ideal voltage controlled current

source. The resistor Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The

1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency

response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting

a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by

replacing the R

with a current source with the appropriate load step amplitude and step rate in a time domain

analysis.

Product Folder Links: TPS54418