Datasheet

O
0.8 V
R2 = R1
V 0.8 V
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TPS54418
www.ti.com SLVS946C –MAY 2009–REVISED JULY 2013
DETAILED DESCRIPTION
FIXED FREQUENCY PWM CONTROL
The TPS54418 uses an adjustable fixed-frequency peak-current-mode control. The output voltage is compared
through external resistors on the VSENSE to pin an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output
is compared to the high-side power-switch current. When the power switch reaches the COMP voltage, the high-
side power switch is turned off and the low-side power switch is turned on.
The COMP pin voltage increases and decreases as the peak switch current increases and decreases. The
device implements a current-limit function by clamping the COMP pin voltage to a maximum value, which limits
the maximum peak current the device will supply. The device also implements a minimum COMP voltage clamp
for improved transient response. When the COMP voltage is pushed low to the minimum clamp, such as during a
load release event, turnon of the high-side power switch is inhibited.
SLOPE COMPENSATION AND OUTPUT CURRENT
The TPS54418 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-
harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the full
duty cycle range.
BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION
The TPS54418 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended because of the stable characteristics over temperature and voltage.
To improve drop out, the TPS54418 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.5 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low
side MOSFET to conduct when the voltage from BOOT to PH drops below 2.5 V. Since the supply current
sourced from the BOOT pin is very low, the high side MOSFET can remain on for more switching cycles than are
required to refresh the capacitor, thus the effective duty cycle of the switching regulator is very high.
ERROR AMPLIFIER
The TPS54418 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower
of the SS pin voltage or the internal 0.8 V voltage reference. The transconductance of the error amplifier is 225
μA/V during normal operation. When the voltage of VSENSE pin is below 0.8 V and the device is regulating
using the SS voltage, the gm is 70 μA/V. The frequency compensation components are placed between the
COMP pin and ground.
VOLTAGE REFERENCE
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit. The bandgap and scaling circuits produce 0.8 V at the non-inverting
input of the error amplifier.
ADJUSTING THE OUTPUT VOLTAGE
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use divider resistors with 1% tolerance or better. Start with a 100 kΩ for the R1 resistor and use the Equation 1
to calculate R2. To improve efficiency at very light loads consider using larger value resistors. If the values are
too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are
noticeable.
(1)
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