Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder WQFN 16

VIN

POWERPAD

BOOT

VSENSE

COMP

TPS54418

RT /CLK

PWRGD

BOOT

VOUT

VIN

AGND

GND

100

0 0.5 1 1.5 2 2.5 3 3.5 4

V =5V,

V =1.8V,

fsw=500kHz

Efficiency-%

LoadCurrent- A

TPS54418

www.ti.com

SLVS946C –MAY 2009–REVISED JULY 2013

2.95 V to 6 V Input, 4 A Output, 2 MHz, Synchronous Step Down

Switcher With Integrated FETs ( SWIFT™)

FEATURES

DESCRIPTION

• Two 30 mΩ (typical) MOSFETs for high

The TPS54418 device is a full featured 6 V, 4 A,

efficiency at 4 A loads

synchronous step down current mode converter with

• 200kHz to 2MHz Switching Frequency

two integrated MOSFETs.

• 0.8 V ± 1% Voltage Reference Over

The TPS54418 enables small designs by integrating

Temperature

the MOSFETs, implementing current mode control to

• Synchronizes to External Clock

reduce external component count, reducing inductor

size by enabling up to 2 MHz switching frequency,

• Adjustable Slow Start/Sequencing

and minimizing the IC footprint with a small 3mm x

• UV and OV Power Good Output

3mm thermally enhanced QFN package.

• Low Operating and Shutdown Quiescent

The TPS54418 provides accurate regulation for a

Current

variety of loads with an accurate ±1% Voltage

• Safe Start-up into Pre-Biased Output

Reference (VREF) over temperature.

• Cycle by Cycle Current Limit, Thermal and

Efficiency is maximized through the integrated 30mΩ

Frequency Fold Back Protection

MOSFETs and 350μA typical supply current. Using

• –40°C to 150°C Operating Junction

the enable pin, shutdown supply current is reduced to

Temperature Range

2 μA by entering a shutdown mode.

• Thermally Enhanced 3mm × 3mm 16-pin QFN

Under voltage lockout is internally set at 2.6 V, but

can be increased by programming the threshold with

APPLICATIONS

a resistor network on the enable pin. The output

voltage startup ramp is controlled by the slow start

• Low-Voltage, High-Density Power Systems

pin. An open drain power good signal indicates the

• Point of Load Regulation for High Performance

output is within 93% to 107% of its nominal voltage.

DSPs, FPGAs, ASICs and Microprocessors

Frequency fold back and thermal shutdown protects

• Broadband, Networking and Optical

the device during an overcurrent condition.

Communications Infrastructure

The TPS54418 is supported in the SwitcherPro

SIMPLIFIED SCHEMATIC

Software Tool at www.ti.com/switcherpro.

For more SWIFT

documentation, see the TI

website at www.ti.com/swift.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 2.95 V to 6 V Input, 4 A Output, 2 MHz, Synchronous Step Down Switcher With Integrated FETs ( SWIFT™) FEATURES 1 • 2 • • • • • • • • • • Two 30 mΩ (typical) MOSFETs for high efficiency at 4 A loads 200kHz to 2MHz Switching Frequency 0.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TJ PACKAGE PART NUMBER –40°C to 150°C 3 × 3 mm QFN TPS54418RTE ABSOLUTE MAXIMUM RATINGS Input voltage VALUE UNIT VIN –0.3 to 7 V EN –0.3 to 7 BOOT PH + 8 VSENSE –0.3 to 3 COMP –0.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 2.6 2.8 V 2 5 μA 350 500 μA 1.25 1.37 V SUPPLY VOLTAGE (VIN PIN) Operating input voltage 2.95 Internal under voltage lockout threshold No voltage hysteresis, rising and falling Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V Quiescent Current - Iq VSENSE = 0.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT BOOT (BOOT PIN) BOOT Charge Resistance VIN = 5 V 16 Ω BOOT-PH UVLO VIN = 2.95 V 2.1 V Charge Current V(SS) = 0.4 V 1.8 μA SS to reference crossover 98% nominal 0.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 DEVICE INFORMATION PIN CONFIGURATION 2 GND 3 GND 4 EN PWRGD BOOT 14 13 Thermal Pad (17) AGND 5 6 7 8 RT/CLK VIN 15 COMP 1 16 VSENSE VIN VIN QFN16 RTE PACKAGE (TOP VIEW) 12 PH 11 PH 10 PH 9 SS PIN FUNCTIONS PIN NAME DESCRIPTION NO. AGND 5 Analog Ground should be electrically connected to GND close to the device. BOOT 13 A bootstrap capacitor is required between BOOT and PH.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 TYPICAL CHARACTERISTICS CURVES (continued) HIGH SIDE CURRENT LIMIT vs TEMPERATURE VOLTAGE REFERENCE vs TEMPERATURE 7 6.9 0.808 VIN = 3 .3 V VIN = 3 V 0.806 Vref - Voltage Reference - V High Side Switch Current - A 6.8 6.7 6.6 6.5 6.4 6.3 6.2 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 0.798 0.796 -25 0 125 Figure 4.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) TRANSCONDUCTANCE (SLOW START) vs JUNCTION TEMPERATURE ENABLE PIN VOLTAGE vs TEMPERATURE 1.3 90 85 VIN = 3 .3 V 1.29 1.28 EA - Transconductance - mA/V VIN = 3.3 V, rising 1.27 80 1.26 EN - Threshold - V 75 70 65 60 55 1.25 1.24 1.23 1.22 1.21 1.2 VIN = 3.3 V, falling 1.19 1.18 50 1.17 45 40 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 1.16 1.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 TYPICAL CHARACTERISTICS CURVES (continued) INPUT VOLTAGE vs TEMPERATURE SHUTDOWN SUPPLY CURRENT vs TEMPERATURE 3 3 VIN = 3.3 V 2.9 2.5 2.7 Shutdown Supply Current - mA VIN - Input Voltage - V 2.8 UVLO Start Switching 2.6 2.5 UVLO Stop Switching 2.4 2.3 2.2 2 1.5 1 0.5 2.1 2 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 0 -50 150 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 15. 125 150 Figure 16.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) MINIMUM COMP VOLTAGE CLAMP vs TEMPERATURE 1 200 180 Typical 0.8 160 140 120 100 80 60 0.6 0.5 0.4 0.3 0.2 20 0.1 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 +3 Sigma 0.7 40 0 -50 ±3 Sigma 0.9 VIN = 3.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 DETAILED DESCRIPTION FIXED FREQUENCY PWM CONTROL The TPS54418 uses an adjustable fixed-frequency peak-current-mode control. The output voltage is compared through external resistors on the VSENSE to pin an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output is compared to the high-side power-switch current.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com TPS54418 VO R1 VSENSE R2 0.8 V + Figure 23. Voltage Divider Circuit ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT The TPS54418 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 24 to adjust the input voltage UVLO by using two external resistors. It is recommended to use the enable resistors to set the UVLO falling threshold (VSTOP) above 2.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.2 V, or a thermal shutdown event occurs, the TPS54418 stops switching and the SS is discharged to 0 volts before reinitiating a powering up sequence. SEQUENCING Many of the common power supply sequencing methods can be implemented using the SS, EN and PWRGD pins.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin) The switching frequency of the TPS54418 is adjustable over a wide range from 200 kHz to 2000 kHz by placing a maximum of 1000kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is typically 0.5 V.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 TPS54418 SYNC Clock = 2 V / div PLL PH = 2 V / div RT/CLK Clock Source RT Time = 500 nsec / div Figure 29. Synchronizing to a System Clock Figure 30. Plot of Synchronizing to System Clock POWER GOOD (PWRGD PIN) The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters the fault condition by falling below 91% or rising above 107% of the nominal internal reference voltage.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com PH VO Power Stage 13.0 A/V a b R1 c R3 C2 RESR RL COMP 0.8 V CO RO VSENSE gm 225 uA/V C1 COUT R2 Figure 31. Small Signal Model for Loop Response SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL Figure 31 is a simple small signal model that can be used to understand how to design the frequency compensation.
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TPS54418 www.ti.com ¦p = ¦z = SLVS946C – MAY 2009 – REVISED JULY 2013 1 C OUT ´ R L ´ 2 p COUT (9) 1 ´ RESR ´ 2p (10) SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION The TPS54418 uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 33. The Type 2 circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com APPLICATION INFORMATION DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the HPA375 evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 For this design example, use KIND = 0.3 and the inductor value is calculated to be 0.96 μH. For this design, a nearest standard value was chosen: 1.0 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 20 and Equation 21. For this design, the RMS inductor current is 4.014 A and the peak inductor current is 4.58 A.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 24 indicates the ESR should be less than 26 mΩ. In this case, the ESR of the ceramic capacitor is much less than 26 mΩ. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 SLOW START CAPACITOR The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com RDS = minimum high side MOSFET on resistance (30 - 44 mΩ) RL = series resistance of output inductor (32) There is also a maximum acheivable output voltage which is limited by the minimum off time.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 From the procedures above, the compensation network includes a 7.5 kΩ resistor and a 2700 pF capacitor. APPLICATION CURVES EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 100 100 3.3 Vin,1.8 Vout 95 90 90 80 3.3 Vin,1.8 Vout Efficiency - % 5 Vin, 1.8 Vout Efficiency - % 85 80 75 70 60 5 Vin, 1.8 Vout 50 40 70 30 65 20 60 10 0 0.001 55 0.01 0.1 Output Current - A 50 0 1 2 3 1 10 4 Output Current - A Figure 35.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com POWER UP VOUT, EN POWER DOWN VOUT, EN Vin = 5 V / div Vin = 5 V / div EN = 2 V / div EN = 2 V / div SS = 2 V / div SS = 2 V / div Vout = 2 V / div Vout = 2 V / div Time = 5 msec / div Time = 5 msec / div Figure 41. Figure 42. OUTPUT RIPPLE, 0 A OUTPUT RIPPLE, 4 A Vout = 10 mV / div (ac coupled) Vout = 10 mV / div (ac coupled) PH = 2 V / div PH = 2 V / div Time = 500 nsec / div Time = 500 msec / div Figure 43. Figure 44.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 LOAD REGULATION vs LOAD CURRENT CLOSED LOOP RESPONSE, VIN (3.3 V), 4 A 60 180 50 150 90 20 60 10 30 Gain 0.1 0 -10 -30 -20 -60 -30 -90 -40 -120 -50 -150 -60 -180 0.05 0 -0.05 -0.1 -0.15 -0.2 1000000 100000 10000 1000 100 Frequency - Hz Percent Deviation - % 30 0 Vin = 3.3 0.15 120 Phase Phase - Deg Gain 40 0.2 0 1 2 3 4 Output Current - A Figure 47. Figure 48.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com ƒsw is the switching frequency (Hz). So Ptot = Pcon + Pd + Psw + Pgd + Pq For given TA, TJ = TA + Rth × Ptot For given TJMAX = 150°C TAmax = TJ max – Rth × Ptot Where: Ptot is the total device power dissipation (W). TA is the ambient temperature (°C). TJ is the junction temperature (°C). Rth is the thermal resistance of the package (°C/W). TJMAX is maximum junction temperature (°C). TAMAX is maximum ambient temperature (°C).
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 TAmax - Maximum Ambient Temperature - C 150 140 130 Tjmax = 150 °C, no air flow 120 110 100 90 80 70 60 50 40 30 20 0 0.5 1 1.5 2 2.5 3 3.5 Power Dissapated (W) Figure 52. Maximum Ambient Temperature vs IC power Dissipation LAYOUT Layout is a critical portion of good power supply design.
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TPS54418 SLVS946C – MAY 2009 – REVISED JULY 2013 www.ti.com VIA to Ground Plane UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR BOOT PWRGD EN VIN VIN BOOT CAPACITOR VIN OUTPUT INDUCTOR PH VIN PH EXPOSED POWERPAD AREA GND PH GND PH VOUT OUTPUT FILTER CAPACITOR SLOW START CAPACITOR RT/CLK COMP VSENSE AGND SS FEEDBACK RESISTORS ANALOG GROUND TRACE FREQUENCY SET RESISTOR TOPSIDE GROUND AREA COMPENSATION NETWORK VIA to Ground Plane Figure 53.
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TPS54418 www.ti.com SLVS946C – MAY 2009 – REVISED JULY 2013 REVISION HISTORY Changes from Revision A (May 2010) to Revision B • Page Added "Instantaneous peak current" to the Current Limit in the Electrical Characteristics table ......................................... 3 Changes from Revision B (August 2012) to Revision C Page • Added Minimum Comp Voltage Clamp vs Temperature graph to TYPICAL CHARACTERISTIC CURVES .......................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54418RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54418RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54418RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54418RTER WQFN RTE 16 3000 367.0 367.0 35.0 TPS54418RTET WQFN RTE 16 250 210.0 185.0 35.0 TPS54418RTET WQFN RTE 16 250 210.0 185.0 35.
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