Datasheet

2.9 Powering Up
Vin=5V/div
EN=2V/div
SS=2V/div
Vout=2V/div
Time=5msec/div
Vin=5V/div
EN=2V/div
SS=2V/div
Vout=2V/div
Time=5msec/div
3 Board Layout
3.1 Layout
www.ti.com Board Layout
Figure 9 and Figure 10 show the start-up waveforms for the TPS54418EVM-375. In Figure 9 , the output
voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R
1
and R
2
resistor divider network. In Figure 10 , the input voltage is initially applied and the output is inhibited by
using a jumper at J2 to tie EN to GND. When the jumper is removed, EN is released. When the EN
voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps
up to the externally set value of 1.8 V. The input voltage for these plots is 5 V and the load is 1 Ω .
Figure 9. TPS54418EVM-375 Start-Up Relative to V
IN
Figure 10. TPS54418EVM-375 Start-up Relative to Enable
This section provides a description of the TPS54418EVM-375, board layout, and layer illustrations.
Figure 11 through Figure 15 shows the board layout for the TPS54418EVM-375. The topside layer of the
EVM is laid out in a manner typical of a user application. The top, bottom and internal layers are 2-oz.
copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. Also on the top layer are
SLVU280 – May 2009 TPS54418EVM-375 4-A, SWIFT™ Regulator Evaluation Module 9
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