Datasheet

SW1
VIN1
VBST1
EN1
VFB1
GND
VREG 5
PGND1
6
VIN2
VBST2
EN2
SW2
PG1
5
1
3
PG2
9
10
11
PGND2
2
4
7
13
12
14
8
15
16
VFB2
VIN2
BIAS
CAP
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
～0.1µF
VIN INPUT
BYPASS
CAPACITOR
10µF x2
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
POWER
GND
TO ENABLE
CONTROL
Keep
distance more
than
1
inch
Recommend to keep
distance more than 3-4mm.
(to avoid noise scattering,
especially GND plane.)
To feedback
resisters
VO2
Feedback
resisters
GND
PLANE
2
,3 or bottom
layer
Symmetrical Layout
for CH1 and CH2
Switching noise
flows through IC
and C
IN
. It avoids
the thermal Pad
.
Via to GND Plane
- Blue parts can be placed on the bottom side
- Connect the SWx pins through another layer with the inductor
(yellow line)
TPS54394
SLVSBE6B –JUNE 2012–REVISED AUGUST 2013 www.ti.com
7. Exposed pad of device must be soldered to PGND.
8. VREG5 capacitor should be placed near the device, and connected to GND.
9. Output capacitors should be connected with a broad pattern to the PGND.
10. Voltage feedback loops should be as short as possible, and preferably with ground shields.
11. Kelvin connections should be brought from the output to the feedback pin of the device.
12. Providing sufficient vias is preferable for VIN, SW and PGND connections.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
Figure 26. TPS54394 Layout
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