Datasheet

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0
0.4
0.6
0.8
1.0
1.8
0.2
0 20 40 60 14080 100 120
T
A
- Ambient Temperature - °C
P
D
- Power Dissipation - W
0
150
250
500
LFM
1.2
1.6
1.4
LFM = 0
LFM = 150
LFM = 250
LFM = 500
PowerPAD Package
PCB Layout Guidelines
TPS54383 , , TPS54386
SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007
POWER DISSIPATION
vs
AMBIENT TEMPERATURE
Figure 36. Power Derating Curves
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend
on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and
should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via
is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the
package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13
mils) work well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel of
the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material
should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping
prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the
package. (See the Additional References section.)
The layout guidelines presented here are illustrated in the PCB layout examples given in Figure 37 and
Figure 38 .
• The PowerPAD must be connected to a low current (signal) ground plane having a large copper surface area
to dissipate heat. Extend the copper surface well beyond the IC package area to maximize thermal transfer of
heat away from the IC.
• Connect the GND pin to the PowerPAD through a 10-mil (.010 in, or 0.0254 mm) wide trace.
• Place the ceramic input capacitors close to PVDD1 and PVDD2; connect using short, wide traces.
• Maintain a tight loop of wide traces from SW1 or SW2 through the switch node, inductor, output capacitor and
rectifier diode. Avoid using vias in this loop.
• Use a wide ground connection from the input capacitor to the rectifier diode, placed as close to the power
path as possible. Placement directly under the diode and the switch node is recommended.
• Locate the bootstrap capacitor close to the BOOT pin to minimize the gate drive loop.
• Locate voltage setting resistors and any feedback components over the ground plane and away from the
switch node and the rectifier diode to input capacitor ground connection.
30 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS54383 TPS54386