Datasheet

www.ti.com
f
EQ ESR(zero)
1
C1
2 R
=
p´ ´
(5)
EQ
1
R R3
1 1
R1 R2
= +
æ ö
æ ö æ ö
+
ç ÷
ç ÷ ç ÷
è ø è ø
è ø
(6)
f
EQ POLE(desired)
1
C1
2 R
=
p´ ´
(7)
EQ
1
R R3
1 1
R1 R2
= +
æ ö
æ ö æ ö
+
ç ÷
ç ÷ ç ÷
è ø è ø
è ø
(8)
( )
( )
f
C
1 R1
C2 1
2 R1
R2 R3
R2 R3
= ´ +
p´ ´
æ ö
´
ç ÷
ç ÷
+
è ø
(9)
TPS54383 , , TPS54386
SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007
The value of the capacitor is calculated in Equation 5 .
where:
• R
EQ
is an equivalent impedance created by the parallel combination of the voltage setting divider resistors (R1
and R2) in series with R3.
Using All Ceramic Output Capacitors
With low ESR ceramic capacitors, there may not be enough phase margin at the crossover frequency. In this
case, (Ref Figure 30 ) resistor R3 is set equal to 1/2 R2. This lowers the gain by 6 dB, reduce the crossover
frequency, and improve phase margin.
The value of C1 is found by determining the frequency to place the low frequency pole. The minimum frequency
to place the pole is 1 kHz. Any lower, and the time constant will be too slow and interfere with the internal soft
start. (Ref. Soft Start ) The upper bound for the pole frequency is determined by the operating frequency of the
converter. It is 3 kHz for the TPS54x83, and 6 kHz for the TPS54x86. C1 is then found from Equation 7 . Keep
component tolerances in mind when selecting the desired pole frequency.
where:
• f
POLE(desired)
is the desired pole frequency between 1 kHz and 3 kHz (TPS54x83) or 1 kHz and 6 kHz
(TPS54x86).
• R
EQ
is an equivalent impedance created by the parallel combination of the voltage setting divider resistors (R1
and R2) in series with R3.
If it is necessary to increase phase margin, place a capacitor in parallel with the upper voltage setting divider
resistor (Ref. C2 in Equation 9 ).
where
• f
C
is the unity gain crossover frequency, (approximately 50 kHz for most designs following these guidelines)
22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS54383 TPS54386