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Output Voltage Regulation
V
REF
V
OUT
- V
REF
R2=R1´
(2)
1
2
3
4
14
13
12
11
PVDD2
BOOT2
SW2
BP
PVDD1
BOOT1
SW1
GND
TPS5438x
5
6
7
10
9
8
SEQ
ILIM2
FB2
EN1
EN2
FB1
R1
OUTPUT1
R2
UDG-07011
TPS54383 , , TPS54386
SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007
to support the desired regulation voltage by the time Soft Start has completed, then
the output UV circuit may trip and cause a hiccup in the output voltage. In this case,
use a timed delay startup from the ENx pin to delay the startup of the output until the
PVDDx voltage has the capability of supporting the desired regulation voltage. See
Operating Near Maximum Duty Cycle and Maximum Output Capacitance for related
information.
Each output has a dedicated feedback loop comprised of a voltage setting divider, an error amplifier, a pulse
width modulator, and a switching MOSFET. The regulation output voltage is determined by a resistor divider
connecting the output node, the FBx pin, and GND (see Figure 21 ). Assuming the value of the upper voltage
setting divider is known, the value of the lower divider resistor for a desired output voltage is calculated by
Equation 2 .
where
• V
REF
is the internal 0.8-V reference voltage
Figure 21. Feedback Network for Channel 1
DESIGN HINT
There is a leakage current of up to 12 µ A out of the SW pin when a single output of
the TPS5438x is disabled. Keeping the series impedance of R1 + R2 less than 50 k Ω
prevents the output from floating above the referece voltage while the controller output
is in the OFF state.
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