Datasheet

TPS54380

SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005

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AGND

VSENSE

COMP

PWRGD

BOOT

ENA

TRACKIN

VBIAS

VIN

PGND

PWP PACKAGE

(TOP VIEW)

THERMAL

PAD

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME NO.

DESCRIPTION

AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor.

Connect PowerPAD to AGND.

BOOT 5 Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-side FET driver.

COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE

ENA 19 Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and

places device in low quiescent current state.

PGND 11−13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas

to the input and output supply returns, and negative terminals of the input and output capacitors. A single-point connection

to AGND is recommended.

PH 6−10 Phase output. Junction of the internal high-side and low-side power MOSFETs and output inductor.

PWRGD 4 Power-good open-drain output. High when VSENSE ≥ 90% V

ref

, otherwise PWRGD is low.

RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.

TRACKIN 18 External reference input. High impedance input to internal reference/multiplexer and error amplifier circuits.

VBIAS 17 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.

VIN

14−16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device

package with a high quality, low-ESR 10-µF ceramic capacitor.

VSENSE 2 Error amplifier inverting input. Connect to output voltage through compensation network/output divider.