Datasheet

Powering Up and Down
2-10
2.9 Powering Up and Down
The TPS54380 regulator provides different modes for power up and power
down sequencing of the core and I/O voltages. By selecting the different ratios
for the resistor divider R6/R7 (Figure 4–1), the slope of core voltage during
powering up and down can be set equal to, higher than, or lower than the slope
of I/O voltage. If the resistors R6 = R1 and R7 = R2, then the core voltage tracks
the I/O voltage. The start-up voltage waveform of the TPS54380EVM-001 for
this condition is shown in Figure 2–11. The waveform shows that the core
voltage regulator tracks the output of I/O regulator until the core regulator
reaches its nominal 1.8-V level. After that, the core regulator starts to regulate
its output at the preset 1.8-V level. The I/O regulator continues its ramp up until
the voltage reaches the nominal 3.3-V level. The output voltage waveforms
during powering up do not depend on load currents. The output voltage
waveforms are powered up by asserting the ENABLE signal, while the input
voltage is already applied.
Figure 2–11. Power Up With Tracking
V
O
I/O 500 mV/div
Time Scale 500 µs/div
V
O
CORE 500 mV/div
The power-down waveform is shown in Figure 2–12. During power down, the
output voltage fall time is defined by the output capacitance and load
resistance. In this case the I/O output load resistance has been set to 20 Ω and
the core output load resistance set to 1 Ω. With the I/O output voltage falling
with a slew rate of about 1.25 V/ms, there is essentially no difference between
the core voltage and I/O voltage.