! User’s Guide June 2003 PMP Systems Power SLVU087
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 3 V to 5 V and the output voltage range of 0.9 V to 3.3 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Preface About This Manual This user’s guide describes the characteristics, operation and use of the TPS54380EVM evaluation module (EVM). The user’s guide includes a schematic diagram, printout-circuit board (PCB) layouts, and bill of materials. How to Use This Manual - Chapter 1—Introduction - Chapter 2—Test Setup and Results - Chapter 3—Board Layout - Chapter 4—Schematic and Bill of MAterials Information About Cautions and Warnings This book may contain cautions and warnings.
Information About Cautions and Warnings Trademarks SWIFT is a trademark of Texas Instruments. PowerPAD is a trademark of Texas Instruments.
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Figures 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 2–16 3–1 3–2 3–3 4–1 Frequency Trimming Resistor Selection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Measured Efficiency, TPS54380 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 Introduction This chapter contains background information for the TPS54380 as well as support documentation for the TPS54380EVM-001 evaluation module (HPA001). The TPS54380EVM-001 performance specifications are given, with the schematic and bill of material for the TPS54380EVM-001. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . .
Background 1.1 Background The TPS54380 tracking dc/dc converter provides accurate power sequencing in applications where two or more voltages are required for a load. These types of applications include core and I/O power supplies for microprosessors, DSPs, and FPGAs. Typically, some specific relation between the core and I/O supply voltages has to be provided during the power-up and power-down sequences.
Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54380EVM-225 performance specifications is provided in Table 1–2. Specifications are given for an input voltage of 3.3 V and an output voltage of 1.8 V unless otherwise specified. The ambient temperature is 25°C for all measurements, unless otherwise noted. The data presented in Table 1–2 compiled with no load on the I/O output. The input voltage range is limited to 5.5 V by the distribution switch.
Modifications 1.3 Modifications The TPS54380EVM–001 is designed to demonstrate the small size that can be attained when designing with the TPS54380, so many of the features, which allow for extensive modifications have been omitted from this EVM. Changing the value of R2 can change the output voltage in the range of 0.9 V to 3.3 V. The value of R2 for a specific output voltage can be calculated by using Equation 1–1. Table 1–3 list the values for R2 for some common output voltages. Equation 1–1.
Modifications Figure 1–1. Frequency Trimming Resistor Selection Graph 750 700 Switching Frequency – kHz 650 600 550 500 450 400 350 300 250 60 70 80 90 100 110 120 130 140 150 160 170 180 Resistance – kΩ An onboard electrolytic input capacitor may be added at C1. 1.3.1 Power Sequencing By selecting different R6–R7 resistor divider ratios, different power sequencing scenarios can be set. The equations 1–3, 1–4 and 1–5 below show how to select the different ways of power sequencing. Equation 1–3.
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Chapter 2 Test Setup and Results This chapter describes how to properly connect, set up, and use the TPS54380EVM-001 evaluation module. The chapter also includes test results typical for the TPS54380EVM-001 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and start up. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The TPS54380EVM-001 has the following three input/output connectors: VI J1, VO I/O J2 and VO Core J3. A diagram showing the connection points is shown in Figure 2–1. A power supply capable of supplying 5 A is connected to J1 through a pair of 20 AWG wires. The load is connected to J2 through a pair of 16 AWG wires. The maximum load current capability should be 3 A. Wire lengths are minimized to reduce losses in the wires.
Efficiency 2.2 Efficiency The TPS54380EVM–001 efficiency peaks at load current of about 1 A to 2 A, and then decreases as the load current increases towards full load. Figure 2–2 shows the efficiency for the TPS54380 at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the MOSFETs.
Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with a good board layout, allows the TPS54380EVM-001 EVMs to output full rated load current while maintaining safe junction temperatures. With a 3.3-V input source and a 3-A load, the junction temperature is approximately 60°C, while the case temperature is approximately 55°C. The total circuit losses at 25°C are shown in Figure 2–3. Power dissipation is shown for input voltages of 3.3 V and 5.0 V.
Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the TPS54380EVM–001 is shown in Figure 2–4, while the output voltage line regulation is shown in Figure 2–5. Measurements are given for an ambient temperature of 25°C. Figure 2–4. Load Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT 0.5 VO – Output Voltage Change – % 0.4 0.3 0.2 0.1 VI = 3.3 V 0 –0.1 VI = 5 V –0.2 –0.3 –0.4 –0.5 0 0.5 1 1.5 2 2.5 IO – Output Current – A 3 3.5 Figure 2–5.
Load Transients 2.5 Load Transients The TPS54380EVM–001 response to load transients is shown in Figure 2–6. The current step is from 25% to 75% of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2–6.
Loop Characteristics 2.6 Loop Characteristics The TPS54380EVM–001 loop response characteristics are shown in Figure 2–7 and Figure 2–8. Gain and phase plots are shown for each device at minimum and maximum operating voltage. Figure 2–7. Measured Loop Response, TPS54380, VI = 3 V MEASURED LOOP RESPONSE 60 180 50 150 120 40 Phase 30 90 Gain – dB 10 Gain 30 0 0 –10 –30 –20 –60 –30 –90 –40 –120 –50 –150 –60 100 1k 10 k Phase – deg 60 20 –180 1M 100 k f – Frequency – Hz Figure 2–8.
Output Voltage Ripple 2.7 Output Voltage Ripple The TPS54X73EVM–225 output voltage ripple is shown in Figure 2–9. The input voltage is 3.3 V for the TPS54380. Output current is the rated full load of 3 A. Voltage is measured directly across output capacitors. Figure 2–9.
Input Voltage Ripple 2.8 Input Voltage Ripple The TPS54X73EVM–225 output voltage ripple is shown in Figure 2–10. The input voltage is 3.3 V for the TPS54380. Output current for each device is rated full load of 3 A. Figure 2–10.
Powering Up and Down 2.9 Powering Up and Down The TPS54380 regulator provides different modes for power up and power down sequencing of the core and I/O voltages. By selecting the different ratios for the resistor divider R6/R7 (Figure 4–1), the slope of core voltage during powering up and down can be set equal to, higher than, or lower than the slope of I/O voltage. If the resistors R6 = R1 and R7 = R2, then the core voltage tracks the I/O voltage.
Powering Up and Down Figure 2–12. Powering Down With Tracking VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 1 ms/div The TPS54380EVM–001 EVM provides the ability to change the slew rate of output voltage of core regulator by using jumper JP2 (see schematic in Figure 4–1). If jumper JP2 is set so that R8 is connected in parallel to R7, ratiometric power sequencing is implemented. For ratiometric sequencing the following condition needs to be met: if R6 = 10 kΩ then R8 II R7 = (R7 × 0.891)/(VI/O – 0.
Powering Up and Down Figure 2–13. Powering Up With Ratiometric Sequencing VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 500 µs/div Figure 2–14. Powering Down With Ratiometric Sequencing VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 1 ms/div If jumper JP2 is set so that R8 is connected in parallel to R6, the core voltage rises first during powering up and falls second during power down. The waveforms with this type of sequencing are shown in Figure 2–15 and Figure 2–16.
Powering Up and Down Figure 2–15. Powering Up With Core Voltage Rising First VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 500 µs/div Figure 2–16.
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Chapter 3 Board Layout This chapter provides a description of the TPS54380EVM–001 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the TPS54380EVM-001 is shown in Figure 3–1 through Figure 3–3. The top-side layer of the TPS54380EVM–001 is laid out in a manner typical of a user application. The top and bottom layers are 1.5 oz. copper. The top layer contains the main power traces for VI, VO, and V(phase). Also on the top layer are connections for the remaining pins of the TPS54380 and a large area filled with ground. The bottom layer contains ground and VO copper areas, and some signal routing.
Layout Figure 3–2.
Layout Figure 3–3.
Chapter 4 Schematic and Bill of Materials The TPS54380EVM–001 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 4.1 Schematic The schematic for the TPS54380EVM–001 is shown in Figure 4–1. Figure 4–1. TPS54380EVM–001 Schematic J1 VIN GND TP1 2 1 + TP2 C5 10 µF C1 220 µF C10 0.1 µF 1 2 3 4 U1 TPS2013D OUT GND IN OUT IN OUT EN OUT 8 5 C8 820 pF R5 590 Ω R1 10 kΩ C7 82 pF R3 6.34 kΩ C9 10 µF C6 1500 pF JP1 3.3 V First 1.8 V First R8 6.04 kΩ R6 10 kΩ R7 9.76 kΩ Jumper JP2 Not Used For Tracking Option 4-2 R2 9.76 kΩ C15 1000 pF R4 71.
Bill of Materials 4.2 Bill of Materials Table 4–1 contains the bill of materials for the TPS54380EVM–001. Table 4–1. TPS54380EVM-001 Bill of Materials Count RefDes Description MFR Part Number – C1 Capacitor, POSCAP, 220 µF, 10 V, 40-mΩ, 20% 4 C2, C11, C12, C13 Capacitor, ceramic, 22 µF, 6.3 V, X5R, 20% 1210 Sanyo 10TPB220M Taiyo Yuden JMK325BJ226MN 1 C3 Capacitor, ceramic, 0.047 µF, 25 V, X7R, 10% 603 Std Std 1 C4 2 C5, C9 Capacitor, ceramic, 1.
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