Datasheet

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AGND

VSENSE

COMP

STATUS

BOOT

ENA

REFIN

VBIAS

VIN

PGND

TPS54372

SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005

HTTSOP PowerPAD

(TOP VIEW)

Terminal Functions

TERMINAL DESCRIPTION

NAME NO.

AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and RT

resistor. Connect PowerPAD connection to AGND.

BOOT 5 Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-side FET driver.

COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE

ENA 19 Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation

and places device in a low quiescent current state.

PGND 11-13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper

areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single-point

connection to AGND is recommended.

PH 6-10 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.

RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f

REFIN 18 External reference input. High impedance input to slow-start and error amplifier circuits.

STATUS 4 Open-drain output. Asserted low when VIN < UVLO, VBIAS and internal reference are not settled or the internal

shutdown signal is active. Otherwise STATUS is high.

VBIAS 17 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a

high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.

14-16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to

device package with a high-quality, low-ESR 10-µF ceramic capacitor.

VSENSE 2 Error amplifier inverting input. Connect to output voltage compensation network/output divider.