Datasheet

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DISSIPATION RATINGS
(1) (2)
ELECTRICAL CHARACTERISTICS
TPS54372
SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005
THERMAL IMPEDANCE T
A
= 25 ° C T
A
= 70 ° C T
A
= 85 ° C
PACKAGE
JUNCTION-TO-AMBIENT POWER RATING POWER RATING POWER RATING
20-Pin PWP with solder 26.0 ° C/W 3.85 W
(3)
2.11 W 1.54 W
20-Pin PWP without solder 57.5 ° C/W 1.73 W 0.96 W 0.69 W
(1) For more information on the PWP package, see TI technical brief, literature number SLMA002.
(2) Test board conditions:
a. 3-inch x 3-inch, 4 layers, thickness: 0.062-inch
b. 1.5-oz. copper traces located on the top of the PCB
c. 1.5-oz. copper ground plane on the bottom of the PCB
d. Ten thermal vias (see Recommended Land Pattern in applications section of this data sheet)
(3) Maximum power dissipation may be limited by overcurrent protection.
T
J
= –40 ° C to 125 ° C, V
I
= 3 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
VIN Input voltage range 3.0 6.0 V
f
s
= 350 kHz, RT open, PH pin open 6.2 9.60
I
(Q)
Quiescent current f
s
= 500 kHz, RT = 100 k Ω , PH pin open 8.4 12.8 mA
Shutdown, ENA = 0 V 1 1.4
UNDERVOLTAGE LOCKOUT
Start threshold voltage, UVLO 2.95 3.0 V
Stop threshold voltage, UVLO 2.70 2.80 V
Hysteresis voltage, UVLO 0.14 0.16 V
Rising and falling edge deglitch, UVLO
(1)
2.5 µs
BIAS VOLTAGE
Output voltage, VBIAS I
(VBIAS)
= 0 2.70 2.80 2.90 V
Output current, VBIAS
(2)
100 µA
REGULATION
Line regulation
(1) (3)
I
L
= 1.5 A, f
s
= 350 kHz, T
J
= 85 ° C 0.07 %/V
Load regulation
(1) (3)
I
L
= 0 A to 3 A, f
s
= 350 kHz, T
J
= 85 ° C 0.03 %/A
OSCILLATOR
Internally set free-running frequency RT open 280 350 420 kHz
RT = 180 k Ω (1% resistor to AGND)
(1)
252 280 308
Externally set free-running frequency range RT = 100 k Ω (1% resistor to AGND) 460 500 540 kHz
RT = 68 k Ω (1% resistor to AGND)
(1)
663 700 762
Ramp valley
(1)
0.75 V
Ramp amplitude (peak-to-peak)
(1)
1 V
Minimum controllable on time
(1)
200 ns
Maximum duty cycle
(1)
90%
ERROR AMPLIFIER
Error amplifier open-loop voltage gain 1 k Ω COMP to AGND
(1)
90 110 dB
Error amplifier unity gain bandwidth Parallel 10 k Ω , 160 pF COMP to AGND
(1)
3 5 MHz
Error amplifier common mode input voltage
Powered by internal LDO
(1)
0 VBIAS V
range
Input bias current, VSENSE VSENSE = V
ref
60 250 nA
Output voltage slew rate (symmetric),
1.0 1.4 V/µs
COMP
(1)
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 8
3