Datasheet

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AGND
BOOT
VSENSE
COMP
PWRGD
PH
PH
PH
PH
PH
RT
ENA
REFIN
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
VOUT
PH
Vin
TOPSIDE GROUND AREA
VIA to Ground Plane
ANALOG GROUND TRACE
EXPOSED
COMPENSATION
NETWORK
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
RESISTOR DIVIDER
NETWORK
BIAS CAPACITOR
TRACKING VOLTAGE
POWERPAD
AREA
PERFORMANCE GRAPHS
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4
Efficiency − %
I
O
− Output Current − A
f
s
= 700 kHz,
V
I
= 5 V,
V
O
= 1.25 V
1.245
1.247
1.249
1.251
1.253
1.255
0 1 2 3 4
I
O
− Output Current − A
Load Regulation
f
s
= 700 kHz,
T
A
= 25°C,
V
I
= 5 V,
V
O
= 1.25 V
TPS54372
SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005
Figure 9. PCB Layout for 20-Pin PWP PowerPAD
EFFICIENCY LOAD REGULATION
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 10. Figure 11.
10