Datasheet

Layout
3-2
3.1 Layout
The board layout for the SLVP215 is shown in Figure 3–1 through Figure 3–3.
The SLVP215 is laid out in a fashion to resemble a layer stack-up that may be
encountered in a typical application. The top and bottom layers are 1.5 oz.
copper. The top layer contains the main power traces for V
I
, V
O
, and V
(phase
).
The top layer contains connections for the remaining pins of the TPS54372
and a large area filled with ground. The bottom layer consists entirely of a
ground plane which is tied to the top layer ground are by means of vias
including 10 directly under the TPS54372 device to provide a thermal path
from the PowerPAD land to ground.
The input decoupling capacitors (C4 and C8), bias decoupling capacitor (C9),
and bootstrap capacitor (C6) are all located as close to the IC as possible. In
addition, the compensation components are kept close to the IC, minimizing
noise pickup. The compensation circuit ties to the output voltage at the point
of regulation, a wide trace to the output connector (J2).
Figure 3–1. Top-Side Layout
PowerPAD is a trademark of Texas Instruments.