! User’s Guide July 2002 PMP Systems Power SLUU119
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input and output voltage range specified in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Figures 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 3–1 3–2 3–3 4–1 Frequency Trimming Resistor Selection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured Board Losses . . . . .
Chapter 1 Introduction This chapter contains background information for the TPS54372, as well as support documentation for the TPS54372EVM-215 evaluation module (SLVP215). The SLVP215 performance specifications are provided with the schematic and bill of material. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.
Background 1.1 Background The TPS54372EVM-215 evaluation module uses the TPS54372 tracking/termination synchronous buck regulator to provide an output voltage VTTQ that is one half the voltage VDDQ from a nominal 3.3-V or 5-V input. Rated input voltage and output current range is given in Table 1–1. These evaluation modules are designed to demonstrate the small PCB areas that may be achieved when designing with the TPS54372 regulator.
Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54372EVM-215 performance specifications is provided by Table 1–2. All specifications are given for an ambient temperature of 25°C, unless otherwise noted. Table 1–2. TPS54372EVM-215 Performance Specification Summary Specification Test Conditions Min Typ Max Input voltage range 3 3.3 or 5 6 V Output voltage set point † 1.25 1.75 V Output current range VI = 5 V Line regulation IO = 0 – 6 A 2.
Modifications 1.3 Modifications The TPS54372EVM-215 is designed to demonstrate the small size that can be attained when designing with the TPS54372. Many of the features that allow for extensive modifications have been omitted from this EVM. The output voltage V(TTQ) can be set in the range of 6% of VI to 1.75 V by changing the V(DDQ) voltage input at J3. The output V(TTQ) will track at one half the V(DDQ) voltage. The lower voltage limit is set by the minimum on time of the TPS54372.
Chapter 2 Test Setup and Results This chapter describes how to properly connect, set up, and use the SLVP215 evaluation module. The chapter also includes test results typical for the SLVP215 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up. The ambient temperature is 25°C for all test results unless otherwise noted. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The SLVP215 has the following six input/output connections: input, input return, output V(TTQ), output return, tracking input V(DDQ), and tracking input return. A diagram showing the connection points is shown in Figure 2–1. A power supply capable of supplying 5 A should be connected to J1 through a pair of 20 AWG wires. The load should be connected to J2 through a pair of 20 AWG wires. The maximum load current is ±3 A (current may be source or sink).
Efficiency 2.2 Efficiency The SLVP215 efficiency peaks at load current of about 1.5 A, and then decreases as the load current increases towards full load. The efficiency shown in Figure 2–2 is for 5-V input at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the MOSFETs. The efficiency is slightly lower at 700 kHz than at lower switching frequencies due to the gate and switching losses in the MOSFETs.
Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with a good board layout, allows the SLVP215 EVMs to output full rated load current while maintaining safe junction temperatures. With a 5-V input source and a 3-A load, the junction temperature is approximately 60°C, while the case temperature is approximately 55°C. The total board losses at 25°C are shown in Figure 2–3. Figure 2–3.
Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the SLVP215 is shown in Figure 2–4, while the output voltage line regulation is shown in Figure 2–5. Measurements are given for an ambient temperature of 25°C. Figure 2–4. Load Regulation Figure 2–5. Line Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs INPUT VOLTAGE 1.255 1.253 VO – Output Voltage – V VO – Output Voltage – V IO = 0 A 1.252 1.253 1.251 1.249 1.247 1.245 1.251 IO = 1.
Loop Characteristics 2.6 Loop Characteristics The SLVP215 loop response characteristics are shown in Figure 2–8 and Figure 2–9. Gain and phase plots are shown at minimum and maximum operating voltage. The output current is 1.5 A. Figure 2–8.
Output Voltage Ripple 2.7 Output Voltage Ripple The SLVP215 output voltage ripple is shown in Figure 2–10. The input voltage is 5 V for the TPS54372. Output current is the rated full-load current, 3 A. VO – (AC) 20 mV/div Figure 2–10. Measured Output Voltage Ripple Time Scale 1 µs/div 2.8 Input Voltage Ripple The SLVP215 output voltage ripple is shown in Figure 2–11. The input voltage is 5 V for the TPS54372. Output current is the full-rated load current, 3 A. VO – (AC) 50 mV/div Figure 2–11.
Start-Up 2.9 Start-Up The start-up voltage waveform of the SLVP215 is shown in Figure 2–12. There is approximately a 9-ms delay after the input voltage rises above the 2.9-V start-up voltage threshold until the output voltage begins to ramp up to the final value of 1.25 V. The output voltage tracks the greater of the internal and external slow-start voltages, accounting for the change in ramp rates . VO – 500 mV/div VI – 2 V/DIV Figure 2–12.
Chapter 3 Board Layout This chapter provides a description of the SLVP215 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the SLVP215 is shown in Figure 3–1 through Figure 3–3. The SLVP215 is laid out in a fashion to resemble a layer stack-up that may be encountered in a typical application. The top and bottom layers are 1.5 oz. copper. The top layer contains the main power traces for VI, VO, and V(phase). The top layer contains connections for the remaining pins of the TPS54372 and a large area filled with ground.
Layout Figure 3–2. Bottom-Side Layout (looking from top side) Figure 3–3.
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Chapter 4 Schematic and Bill of Materials The SLVP215 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 4.1 Schematic The schematic for the SLVP215 is shown in Figure 4–1. Figure 4–1. SLVP215 Schematic J1 Vin GND TP2 2 1 C4 10 µF TP9 TP3 TP1 R2 36.5 kΩ 1 2 3 4 5 C2 470 pF C6 0.047 µF C1 12 pF 1 2 U1 TPS54372PWP 6 7 8 9 10 AGND VSENSE COMP RT ENA REFIN STATUS VBIAS BOOT VIN PH VIN PH VIN PH PGND PH PGND PGND PwrPad PH R3 1.21 kΩ 20 19 18 17 16 15 14 13 12 11 C9 1 µF R5 71.5 kΩ R6 10 kΩ C12 0.1 µF R7 10 kΩ C13 0.
Bill of Materials 4.2 Bill of Materials The bill of materials for the SLVP215 is given by Table 4–1. Table 4–1. SLVP215 Bill of Materials Count Ref Des Description Size MFR Part Number 1 C1 Capacitor, ceramic, 12 pF, 50 V, NPO, 5% 603 Panasonic ECU-V1H120JCV 1 C11 Capacitor, ceramic, 1 µF, 16 V, X7R, 10% 1206 Panasonic ECJ-3YB1C105K 2 C12, C13 Capacitor, ceramic, 0.
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