Datasheet
SLVS519A − MAY 2004 − REVISED OCTOBER 2004
www.ti.com
23
Figure 27 is an example of power supply sequencing using
a TPS54356 (U1) to generate an output of 3.3 V, and a
TPS54354 (U2) to generate a 1.8-V output. These output
voltages are typical I/O and core voltages for
microprocessors and FPGAs. In the circuit, the 3.3-V
supply is designed to power up first.
The PWRGD pin of U1 is tied to the ENA pin of U2 so that
the 1.8-V supply starts to ramp up after the 3.3-V supply is
within regulation. Figure 18 shows these start up
sequence waveforms.
Since the RT pin of U1 is floating, the SYNC pin is an
output. This synchronization signal is fed the SYNC pin of
U2. The RT pin of U2 has a 110-kΩ resistor to ground, and
the SYNC pin for this device acts as an input. The 1.8-V
supply operates synchronously with the 3.3-V supply and
their switching node rising edges are approximately 180
degrees out of phase allowing for a reduction in the input
voltage ripple. See Figure 19 for this wave form.
ALTERNATE OUTPUT FILTER DESIGNS
The previous design procedure example demonstrated a
technique to design a 3.3-V power supply using both
aluminum electrolytic and ceramic output filter capacitors.
Other types of output filter capacitors are supported by the
TPS5435x family of dc/dc converters. Figures 26−28 show
designs using other popular capacitor types.
In Figure 28, the TPS54356 shown with a single 100-µF
6-V POSCAP as the output filter capacitor. C10 is a high
frequency bypass capacitor and does not enter into the
design equations. The design procedure is similar to the
previous example except in the design of the output filter.
In the previous example, the output filter LC corner was set
at the first zero in the compensation network, while the
second compensation zero was used to counteract the
output filter pole caused by the interaction of the C2
capacitor ESR with C5. In this design example, the output
LC corner frequency is to be set at the second zero
frequency f
Z2
of the internal compensation network,
approximately 5 kHz, while the first zero is used to provide
phase boost prior to the LC corner frequency.
+
+
Figure 28. 3.3-V Power Supply with Sanyo POSCAP Output Filter Capacitor
Inductor Selection
Using equation 12 and a K
IND
of 0.2, the minimum inductor
value required is 8.98 µH. The closest standard value, 10
µH is selected. RMS and peak inductor currents are the
same as calculated previously.
Capacitor Selection
With the inductor set at 10 µH and a desired corner
frequency of 5 kHz, the output capacitor value is given by:
C
2
1
4p
2
ƒ
Z2
2
L
out
1
4 p
2
5000
2
10
5
101 m
F
Use 100 µF as the closest standard value.
Calculating the RMS ripple current in the output capacitor
using equation 16 yields 156 mA. The POSCAP
6TPC100M capacitor selected is rated for 1700 mA. See
the closed loop response curve for this design in Figure 20.