Datasheet
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
www.ti.com
20
1
VIN
VIN
UVLO
PWRGD
RT
SYNC
ENA
COMP
PWRPAD
17
VSENSE
AGND
PGND
VBIAS
LSG
PH
PH
BOOT
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U1
TPS54350PWP
C9
10
µF
C1
47
µF
+
C3
0.1
µF
C4
1 µF
4
8
Q1
R10
4.7
Ω
C10
3300 pF
1
L1
10 µH
+
C2
100 µF
C6
82 nF
R3
768
Ω
C7
1800 pF
R2
374
Ω
R5
137
Ω
R1
1 k
Ω
C8
33 nF
Power Good 3.3 V
6 V − 18 V
VOUT 3.3 V @ 3 A
1
VIN
VIN
UVLO
PWRGD
RT
SYNC
ENA
COMP
PWRPAD
17
VSENSE
AGND
PGND
VBIAS
LSG
PH
PH
BOOT
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U2
TPS54350PWP
C15
10
µF
C5
0.1
µF
C16
1 µF
4
8
Q2
R9
4.7
Ω
C14
3300 pF
1
L2
10 µH
+
C11
100 µF
C13
82 nF
R6
768
Ω
C17
1800 pF
R7
976
Ω
R11
137
Ω
R12
1 k
Ω
C12
33 nF
R4
10 kΩ
Power Good 1.8 V
VOUT 1.8 V @ 3 A
R13
110 k
Ω
12367
2
5
12367
5
2
Easy 1805 Out of Phase
Synchronization
Q1, Q2: Fairchild Semiconductor FDR6674A
L1, L2: Vishay IHLP-5050CE
C2, C11: Sanyo 6TPC100M
Figure 26. 3.3-V/1.8-V Power Supply With Sequencing
C18
47
µF
Pull up to 3.3 V or 5 V
Figure 26 is an example of power supply sequencing using
two TPS54350s. U1 is used to generate an output of 3.3
V, while the voltage output of U2 is set at 1.8 V, typical I/O
and core voltages for microprocessors and FPGAs. In the
circuit, the 3.3−V supply is designed to power up first. The
PWRGD pin of U1 is tied to the ENA pin of U2 so that the
1.8-V supply starts to ramp up after the 3.3-V supply is
within regulation. Since the RT pin of U1 is floating, the
SYNC pin is an output. This synchronization signal is fed
to the SYNC pin of U2. The RT pin of U2 has a 110-kΩ
resistor to ground, and the SYNC pin for this device acts
as an input. The 1.8-V supply operates synchronously with
the 3.3-V supply and their switching node rising edges are
approximately 180° out of phase allowing for a reduction
in the input voltage ripple. See Figure 19 for this wave
form.