E User’s Guide September 2003 PMP Systems Power SLVU097A
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input and output voltage ranges specified in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
How to Use This Manual Preface About This Manual This user’s guide describes the characteristics, operation, and the use of the TPS54350EVM−235 evaluation module. It covers all pertinent areas involved to properly use this EVM board along with the devices that it supports. The physical PCB layout, schematic diagram, and bill of materials are included.
Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 2−13 3−1 3−2 3−3 3−4 4−1 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Measured Efficiency, TPS54350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Measured Circuit Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 This chapter contains background information for the TPS54350 with support documentation for the TPS54350EVM-235 evaluation module (SLVP235). The TPS54350EVM-235 performance specifications are given, along with a schematic and bill of material for the TPS54350EVM-235. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . .
Background 1.1 Background The TPS54350 dc/dc converter is designed to provide up to 3-A output from a nominal 12-V (6-V to 18-V) input voltage source. Rated input voltage and output current range is given in Table 1−1. This evaluation module is designed to demonstrate the small PCB areas that may be achieved when designing with the TPS54350 regulator and does not reflect the high efficiencies that may be achieved when designing with this part.
Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54350EVM-235 performance specifications is provided in Table 1−2. Specifications are given for an input voltage of 12 V and an output voltage of 3.3 V unless otherwise specified. The ambient temperature is 25_C for all measurements, unless otherwise noted. The maximum input voltage for the TPS54350 is 4.5 V to 20 V.
Modifications 1.3 Modifications The TPS54350EVM−235 is designed to demonstrate the small size that can be attained when designing with the TPS54350, so many of the features, which allow for extensive modifications, have been omitted from this EVM. 1.3.1 Output Voltage Setpoint Changing the value of R2 can change the output voltage in the range of 0.9 V to 5 V. The value of R2 for a specific output voltage can be calculated by using Equation 1−1.
Modifications Table 1−4. Internal UVLO Setting Start Voltage Threshold Stop Voltage Threshold VIN 4.4 V 3.7 V UVLO 1.18 V 1.09 V To set a different set of thresholds, R6 and R7 can be selected using the following equations. Equation 1−3. V R6 + R7 I(start) * R7 UVLO(start) Equation 1−4. V R6 + R7 I(stop) * R7 UVLO(stop) 10 kΩ is a good value for R7. 1.3.5 Synchronization The SYNC pin can be configured as an input or as an output, depending on the configuration of the RT pin.
Modifications The evaluation module provides an external pullup resistor of 10 kΩ (R8), test point TP1 that can be tied to an external 3.3-V or 5-V source and test point TP2 to monitor the power good signal. 1.3.7 Synchronous Low-Side FET The TPS54350EVM-235 is provisioned with a external low-side FET for operation as a synchronous buck regulator. If desired, an external catch diode may be used in place of the FET. The pad for the diode is located on the back side of the PCB.
Chapter 2 This chapter describes how to properly connect, setup, and use the TPS54350EVM−235 evaluation module. The chapter also includes test results typical for the TPS54350EVM−235 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and startup. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The TPS54350EVM−235 has the following two input/output connectors: VI (J1), and VO (J3). A diagram showing the connection points is shown in Figure 2−1. A power supply capable of supplying 5 A should be connected to J1 through a pair of 20 AWG wires. The load should be connected to J2 through a pair of 20 AWG wires. The maximum load current capability should be 3 A. Wire lengths should be minimized to reduce losses in the wires.
Efficiency 2.2 Efficiency The TPS54350EVM−235 efficiency peaks at load current of about 1 A and VI of 6 V, and then decreases as the load current increases towards full load. For higher input voltages, quiescent losses are greater and the efficiency peaks under full load conditions. It is important to consider that this design is optimized for small size and flexibility and does not reflect the high efficiencies that are possible for specific applications using the TPS54350.
Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with a good board layout, allows the TPS54350EVM−235 EVMs to output full rated load current while maintaining safe junction temperatures. With a 12-V input source and a load approaching the current limit of 4.2 A, the junction temperature is approximately 47°C. The total circuit losses at 25°C are shown in Figure 2−3. Power dissipation is shown for input voltages of 6 V, 12 V and 18 V.
Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the TPS54350EVM−235 is shown in Figure 2−4, while the output voltage line regulation is shown in Figure 2−5. Measurements are given for an ambient temperature of 25°C. Figure 2−4. Load Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT VO − Output Voltage Change − % 0.3 0.2 0.1 VI = 6 V VI = 12 V 0 VI = 18 V −0.1 −0.2 −0.3 0 0.5 1 1.5 2 2.5 IO − Output Current − A 3 3.5 Figure 2−5.
Load Transients 2.5 Load Transients The TPS54350EVM−235 response to load transients is shown in Figure 2−6. The current step is from 25% to 75% of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2−6.
Loop Characteristic 2.6 Loop Characteristic The TPS54350EVM−235 loop response characteristics are shown in Figure 2−7 and Figure 2−8. Gain and phase plots are shown for each device at minimum and maximum operating voltage. Figure 2−7. Measured Loop Response, TPS54350, VI = 6 V MEASURED LOOP RESPONSE 60 180 50 150 40 120 Phase 30 90 60 10 Gain 30 0 0 −10 −30 −20 −60 −30 −90 −40 −120 −50 −60 100 −150 Phase − deg Gain − dB 20 −180 1k 10 k 100 k f − Frequency − Hz 1M Figure 2−8.
Output Voltage Ripple 2.7 Output Voltage Ripple The TPS54350EVM−235 output voltage ripple is shown in Figure 2−9. The input voltage is 3.3 V for the TPS54350. Output current is the rated full load of 3 A. Voltage is measured directly across output capacitors. Figure 2−9. Measured Output Voltage Ripple, TPS54350 VO (AC) 20 mV/div Vphase 5 V/div t − Time − 1 µs/div 2.8 Input Voltage Ripple The TPS54350EVM−235 output voltage ripple is shown in Figure 2−10. The input voltage is 3.3 V for the TPS54350.
Gate Drive 2.9 Gate Drive The TPS54350 provides the the gate drive signal for a synchronous low-side FET. This gate drive signal and its relation ship to the PHASE signal is shown in Figure 2−11. Figure 2−11.
Powering Up and Down 2.10 Powering Up and Down The start-up voltage waveform of the TPS54350EVM−235 is shown in Figure 2−12. The waveform shows the nominal 12-V input voltage in Ch. 1, the 3.3-V output ramping up in Ch. 2 and the PWRGD signal in Ch. 3. Note that the PWRGD signal is pulled up externally to 3.3 V. Figure 2−12.
Chapter 3 This chapter provides a description of the TPS54350EVM−235 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the TPS54350EVM−235 is shown in Figure 3−1 through Figure 3−4. The topside layer of the TPS54350EVM−235 is laid out in a manner typical of a user application that is optimized for small size. The top and bottom layers are 1.5 oz. copper. The top layer contains the main power traces for VI, VO, and Vphase. Also, on the top layer are connections for the remaining pins of the TPS54350 and a large area filled with ground.
Layout Figure 3−2. Bottom Side Layout Figure 3−3.
Layout Figure 3−4.
Chapter 4 The TPS54350EVM−235 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J1 4-2 1 2 TP5 TP4 + C1 OPEN C9 10 µF VIN 4.5−21 V Max 6−18 Nom R7 OPEN R6 OPEN R4 OPEN R11 OPEN Pull up 3.3 or 5 V TP1 C6 1800 pF C7 82 nF PwrPd 17 137 Ω R5 R1 1 kΩ C4 1µF S 8 5 4 1 23 6 7 TP8 R3 R2 374 Ω C3 0.1 µ F 768 Ω U1 TPS54350PWP 1 VIN BOOT 16 2 VIN PH 15 3 UVLO PH 14 4 LSG 13 PWRGD 5 12 RT VBIAS 6 PGND 11 SYNC 7 AGND 10 ENA 8 COMP VSENSE 9 TP2 Power Good R8 10 kΩ 33 nF C8 FDR6674A Q1 D1 MBR5340T3 OPEN BACK SIDE C11 3300 pF R10 4.
Bill of Materials 4.2 Bill of Materials The bill of materials for the TPS54350EVM−235 is given by Table 4−1. TPS54350EVM-235 Bill of Materials Count Ref Des Description Size MFR Part Number − C1 Capacitor, aluminum, 100 µF, 35 V, 20%, FC Series 0.335 x 0.
4-4
