Datasheet

Board Layout

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3 Board Layout

This section provides a description of the EVM, board layout, and layer illustrations.

3.1 Layout

The board layout for the EVM is shown in Figure 23 through Figure 27. The top-side layer of the EVM is

laid out in a manner typical of a user application. The top and bottom layers are 2-oz copper.

The top layer contains the main power traces for V

, V

OUT

, and SW. Also on the top layer are connections

for the remaining pins of the TPS54340 and a large area filled with ground. The bottom layer contains

ground and a signal route for the bootstrap capacitor. The top and bottom and internal ground traces are

connected with multiple vias placed around the board including six vias directly under the TPS54340

device to provide a thermal path from the top-side ground plane to the bottom-side ground plane.

The input decoupling capacitors (C2 and C3), bootstrap capacitor (C4), and frequency set resistor (R3)

are all located as close to the IC as possible. In addition, the voltage set-point resistor divider components

are also kept close to the IC. The voltage divider network ties to the output voltage at the point of

regulation, the copper V

OUT

trace past the output connector (J1). For the TPS54340, an additional input

bulk capacitor may be required (C3), depending on the EVM connection to the input supply.

Figure 23. TPS54340EVM-182 Top Assembly and Silkscreen

Using the TPS54340 Step-Down Converter Evaluation Module SLVU794A–October 2012–Revised February 2013

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