Datasheet

f
f f= = =
SW
co p(mod) x
600 kHz
2411 Hz x 26.9 kHz
2 2
f f f= = =
co p(mod) x z(mod)
2411 Hz x 455 kHz 33.1 kHz
( )
f = = =
´ p ´ ´ ´ p ´ W ´ m
Z mod
ESR OUT
1 1
455 kHz
2 R C 2 5 m 70 F
( )
( )
f = = =
´ p ´ ´ ´ p ´ ´ m
OUT max
P mod
OUT OUT
I
3.5 A
2411 Hz
2 V C 2 3.3 V 70 F
æ ö
= = W = W
ç ÷
è ø
OUT
HS LS
V - 0.8 V
3.3 V - 0.8 V
R R x 10.2 k x 31.9 k
0.8 V 0.8 V
= = = W
+ m
+
W
ENA
UVLO2
START ENA
1
UVLO1
V
1.2 V
R 87.8 k
V - V 5.75 V - 1.2 V
1.2 A
I
365 k
R
= = = W
m
START STOP
UVLO1
HYS
V - V
5.75 V - 4.5 V
R 368 k
I 3.4 A
TPS54340
www.ti.com SLVSBK0B –OCTOBER 2012–REVISED MARCH 2014
9.2.2.7 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN terminal of the
TPS54340. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 4.5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of R
UVLO1
and R
UVLO2
between Vin and
ground connected to the EN terminal. Equation 2 and Equation 3 calculate the resistance values necessary. For
the example application, a 365 kΩ between Vin and EN (R
UVLO1
) and a 86.6 kΩ between EN and ground
(R
UVLO2
) are required to produce the 8 V and 6.25 V start and stop voltages.
(38)
(39)
9.2.2.8 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 1, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input
current of the FB terminal, the current flowing through the feedback network should be greater than 1 μA to
maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ.
Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but
may also introduce noise immunity problems.
(40)
9.2.2.9 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒ
p(mod)
, and the ESR zero, ƒ
z1
must be calculated using Equation 41 and
Equation 42. For C
OUT
, use a derated value of 70 μF. Use equations Equation 43 and Equation 44 to estimate a
starting point for the crossover frequency, ƒco. For the example design, ƒ
p(mod)
is 2411 Hz and ƒ
z(mod)
is 455 kHz.
Equation 42 is the geometric mean of the modulator pole and the ESR zero and Equation 44 is the mean of
modulator pole and the switching frequency. Equation 43 yields 33.1 kHz and Equation 44 gives 26.9 kHz. Use
the lower value of Equation 43 or Equation 44 for an initial crossover frequency. For this example, the target ƒco
is 26.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
(41)
(42)
(43)
(44)
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