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User's Guide

SLVU814–November 2012

TPS54339EEVM-056, 3-A, Regulator with Eco-Mode™

Evaluation Module

This user's guide contains information for the TPS54339EEVM-056 evaluation module as well as for the

TPS54339E. Included are the performance specifications, schematic, and the bill of materials of the

TPS54339EEVM-056.

Contents

1 Introduction .................................................................................................................. 3

2 Performance Specification Summary ..................................................................................... 3

3 Modifications ................................................................................................................. 3

3.1 Output Voltage Setpoint ........................................................................................... 3

3.2 Output Filter and Closed-Loop Response ...................................................................... 4

4 Test Setup and Results .................................................................................................... 4

4.1 Input/Output Connections ......................................................................................... 4

4.2 Start-Up Procedure ................................................................................................ 5

4.3 Efficiency ............................................................................................................ 5

4.4 Load Regulation .................................................................................................... 6

4.5 Line Regulation ..................................................................................................... 7

4.6 Closed Loop Response ........................................................................................... 7

4.7 Load Transient Response ........................................................................................ 8

4.8 Output Voltage Ripple ............................................................................................. 8

4.9 Input Voltage Ripple ............................................................................................... 9

4.10 Start-Up ............................................................................................................ 10

4.11 Shut-Down ......................................................................................................... 11

5 Board Layout ............................................................................................................... 12

5.1 Layout .............................................................................................................. 12

6 Schematic, Bill of Materials, and Reference ........................................................................... 15

6.1 Schematic ......................................................................................................... 15

6.2 Bill of Materials .................................................................................................... 16

6.3 Reference .......................................................................................................... 16

List of Figures

1 TPS54339EEVM-056 Efficiency .......................................................................................... 5

2 TPS54339EEVM-056 Light-Load Efficiency............................................................................. 6

3 TPS54339EEVM-056 Load Regulation, V

= 5 V and V

= 12 V. ................................................... 6

4 TPS54339EEVM-056 Line Regulation ................................................................................... 7

5 TPS54339EEVM-056 Closed Loop Response.......................................................................... 7

6 TPS54339EEVM-056 Load Transient Response....................................................................... 8

7 TPS54339EEVM-056 Output Voltage Ripple (I

OUT

= 3 A).............................................................. 8

8 TPS54339EEVM-056 Output Voltage Ripple (I

OUT

= 150 mA) ........................................................ 9

9 TPS54339EEVM-056 Output Voltage Ripple (I

OUT

= 0 A).............................................................. 9

10 TPS54339EEVM-056 Input Voltage Ripple ............................................................................ 10

11 TPS54339EEVM-056 Start-Up Relative to V

with SS............................................................... 10

12 TPS54339EEVM-056 Start-Up Relative to EN with SS .............................................................. 11

Eco-Mode, D-CAP2, eco-mode are trademarks of Texas Instruments.

SLVU814–November 2012 TPS54339EEVM-056, 3-A, Regulator with Eco-Mode™ Evaluation Module

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Summary of content (21 pages)

PAGE 1
User's Guide SLVU814 – November 2012 TPS54339EEVM-056, 3-A, Regulator with Eco-Mode™ Evaluation Module This user's guide contains information for the TPS54339EEVM-056 evaluation module as well as for the TPS54339E. Included are the performance specifications, schematic, and the bill of materials of the TPS54339EEVM-056. 1 2 3 4 5 6 Contents Introduction ..................................................................................................................
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www.ti.com 13 TPS54339EEVM-056 Shut-Down Relative to VIN with SS ........................................................... 11 14 TPS54339EEVM-056 Shut-Down Relative to EN with SS ........................................................... 12 15 Top Assembly .............................................................................................................. 13 16 Top Layer ...................................................................................................................
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Introduction www.ti.com 1 Introduction The TPS54339E is a single, adaptive on-time, D-CAP2™-mode, synchronous buck converter requiring a low external component count. The D-CAP2™ control circuit is optimized for low-ESR output capacitors such as POSCAP, SP-CAP, or ceramic types and features fast transient response with no external compensation. The switching frequency is internally set at a nominal 600 kHz.
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Test Setup and Results www.ti.com Table 3 lists the R1 values for some common output voltages. For higher output voltages of 1.8 V or above, a feedforward capacitor (C4) may be required to improve phase margin. Pads for this component (C4) are provided on the printed-circuit board. Note that the resistor values given in Table 3 are standard values and not the exact value calculated using Equation 1. Table 3. Output Voltages 3.
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Test Setup and Results www.ti.com Table 4. Connection and Test Points (continued) Reference Designator 4.2 Function TP8 Output voltage test point at VOUT connector. TP9 Ground test point at VOUT connector. Start-Up Procedure 1. Ensure that the jumper at JP1 (Enable control) is set from EN to OFF. 2. Apply appropriate VIN voltage to VIN and PGND terminals at J1. 3. Move the jumper at JP1 (Enable control) to cover EN and ON. The EVM enables the output voltage. 4.
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Test Setup and Results www.ti.com Figure 2 shows the efficiency at light loads for the TPS54339EEVM-056 at an ambient temperature of 25°C. 100 90 VIN = 5 V 80 Efficiency - % 70 60 50 40 VIN = 12 V 30 20 10 0 0.001 0.01 0.1 1 10 Output Current - A C002 Figure 2. TPS54339EEVM-056 Light-Load Efficiency 4.4 Load Regulation The load regulation for the TPS54339EEVM-056 is shown in Figure 3. 1 0.8 0.6 Load Regulation - % 0.4 VIN = 5 V 0.2 0 -0.2 VIN = 12 V -0.4 -0.6 -0.8 -1 0 0.5 1 1.5 2 2.
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Test Setup and Results www.ti.com 4.5 Line Regulation The line regulation for the TPS54339EEVM-056 is shown in Figure 4. 0.5 0.4 0.3 Line Rgulation - % 0.2 IOUT = 1.5 A 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 4 8 12 16 20 24 Input Voltage - V C004 Figure 4. TPS54339EEVM-056 Line Regulation 4.6 Closed Loop Response The closed loop response for the TPS54339EEVM-056 is shown in Figure 5. VIN = 12 V, RLOAD = 1 Ω.
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Test Setup and Results 4.7 www.ti.com Load Transient Response The TPS54339EEVM-056 response to load transient is shown in Figure 6. The current step is from 0.5 A to 1.5 A. Total peak-to-peak voltage variation is as shown. VOUT = 20 mV / div (ac coupled) IOUT = 1 A / div Load step = 0.75 - 2.25 A, slew rate = 500 mA / µsec Time = 200 µsec / div Figure 6. TPS54339EEVM-056 Load Transient Response 4.8 Output Voltage Ripple The TPS54339EEVM-056 output voltage ripple is shown in Figure 7.
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Test Setup and Results www.ti.com The TPS54339EEVM-056 output voltage ripple is shown in Figure 8. The output current is 150 mA. VOUT = 20 mV / div (ac coupled) SW = 5 V / div Time = 1 µsec / div Figure 8. TPS54339EEVM-056 Output Voltage Ripple (IOUT = 150 mA) The TPS54339EEVM-056 output voltage ripple is shown in Figure 9. The output current is 0 A (no load). VOUT = 20 mV / div (ac coupled) SW = 5 V / div Time = 5 msec / div Figure 9. TPS54339EEVM-056 Output Voltage Ripple (IOUT = 0 A) 4.
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Test Setup and Results www.ti.com VIN = 50 mV / div (ac coupled) SW = 5 V / div Time = 1 µsec / div Figure 10. TPS54339EEVM-056 Input Voltage Ripple 4.10 Start-Up The TPS54339EEVM-056 start-up waveforms relative to VIN and EN are shown in Figure 11 and Figure 12. RLOAD = 1 Ω. VIN = 10 V / div EN = 10 V / div SS = 5 V / div VOUT = 1 V / div Time = 2 msec / div Figure 11.
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Test Setup and Results www.ti.com VIN = 10 V / div EN = 10 V / div SS = 5 V / div VOUT = 1 V / div Time = 2 msec / div Figure 12. TPS54339EEVM-056 Start-Up Relative to EN with SS 4.11 Shut-Down The TPS54339EEVM-056 shut-down waveforms relative to VIN and EN are shown in Figure 13 and Figure 14. RLOAD = 1 Ω. VIN = 10 V / div EN = 10 V / div SS = 5 V / div VOUT = 1 V / div Time = 2 msec / div Figure 13.
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Board Layout www.ti.com VIN = 10 V / div EN = 10 V / div SS = 5 V / div VOUT = 1 V / div Time = 2 msec / div Figure 14. TPS54339EEVM-056 Shut-Down Relative to EN with SS 5 Board Layout This section provides description of the TPS54339EEVM-056, board layout, and layer illustrations. 5.1 Layout The board layout for the TPS54339EEVM-056 is shown in Figure 15 through Figure 19. The top layer contains the main power traces for VIN, VO, and ground.
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Board Layout www.ti.com Figure 15. Top Assembly Figure 16.
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Board Layout www.ti.com Figure 17. Internal Layer 1 Figure 18.
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Schematic, Bill of Materials, and Reference www.ti.com Figure 19. Bottom Layer 6 Schematic, Bill of Materials, and Reference 6.1 Schematic Figure 20 is the schematic for the TPS54339EEVM-056. TP1 J1 VIN 1 GND 2 TP2 C1 C2 10uF 10uF C3 0.1uF JP1 R3 0 TP4 ON 1 EN 2 OFF 3 TP3 R4 10.0k U1 TPS54339E 7 R1 8.25k 5 VOUT C4 6 TP5 1 8 R5 R2 TP7 C5 0 VIN EN VBST VFB SW VREG5 GND SS THERMAL PAD 2 1 C7 0.1uF 0.47uF 8200pF L1 2.2 uH TP8 VOUT 4 C8 9 D1 C6 22.
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Schematic, Bill of Materials, and Reference 6.2 www.ti.com Bill of Materials Table 5. Bill of Materials RefDes Qty Value Description Size Part Number MFR C1, C2 2 10uF Capacitor, Ceramic, 25V, X5R, 20% 1210 Std Std C3 1 0.1uF Capacitor, Ceramic, 50V, X7R, 10% 1206 Std Std C4, C8 0 Open Capacitor, Ceramic 0603 Std Std C5 1 0.47uF Capacitor, Ceramic, 16V, X7R, 10% 0603 Std Std C6 1 8200pF Capacitor, Ceramic, 25V, X7R , 10% 0603 Std Std C7 1 0.
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EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
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FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
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【Important Notice for Users of this Product in Japan】】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
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EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.