Datasheet

× p × × P
P
1
F =
2 C7 R6 R7
× p × ×
Z
1
F =
2 C7 R6
× p × ×
P
1
C5 =
2 R3 F
× p × ×
CO
1
C4 =
F
2 R3
10
-
×
PWRSTG
G
20
out
EA REF
V
10
R3 =
gm V
100 1000 10000 100000 1000000
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
−180
−150
−120
−90
−60
−30
0
30
60
90
120
150
Frequency (Hz)
Gain (dB)
Gain
Phase
G006
Gain = 3.25 dB @ 50 kHz
TPS5432
SLVSB89A –MARCH 2012–REVISED OCTOBER 2012 www.ti.com
For the TPS5432 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage
transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple
approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that a
reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the
pspice model of SLVM279 apply the values calculated previously to the output filter components of L1, C9 and
C10. Set Rload to the appropriate value. For this design, L1 = 2.2 µH. C8 and C9 use the derated capacitance
value of 22 µF, and the ESR is set to 3 mΩ. The Rload resistor is 1.8 / 1.5 = 1.2 Ω. Now the power stage
characteristic can be plotted as shown in Figure 20.
Figure 20. Power Stage Gain and Phase Characteristics
For this design, the intended crossover frequency is 50 kHz. From the power stage gain and phase plots, the
gain at 50 kHz is 3.25 dB and the phase is -128 degrees. For 60 degrees of phase margin, additional phase
boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider will be
required. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at
crossover. The required value of R3 can be calculated from Equation 18.
(18)
To maximize phase gain, the compensator zero F
Z
is placed one decade below the crossover frequency F
CO
of
50 kHz. The required value for C4 is given by Equation 19.
(19)
To maximize phase gain the high frequency pole F
P
is placed one decade above the crossover frequency F
CO
.
The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. The value for C5 can be
calculated from Equation 20.
(20)
The feed forward capacitor C7, is used to increase the phase boost at crossover above what is normally
available from Type II compensation. It places an additional zero/pole pair located at Equation 21 and
Equation 22.
(21)
(22)
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