Datasheet

× p × ×
PMOD
OUT OUT
1
F =
2 C R
×
-
REF
OUT REF
R6 V
R7 =
V V
×C3(nF) = 3 Tss(mS)
Ioutmax 0.25
Vin =
Cin sw
´
D
´ ¦
( )
Vinmin Vout
Vout
Icirm s = Io ut
Vinmin Vinmin
-
´ ´
TPS5432
www.ti.com SLVSB89A –MARCH 2012–REVISED OCTOBER 2012
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vertical spacer
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SLOW START CAPACITOR
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS5432 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start capacitor value can be calculated using Equation 15. For the example circuit, the slow start time is
not too critical since the output capacitor value is 2 x 22 μF which does not require much current to charge to 1.8
V. The example circuit has the slow start time set to an arbitrary value of 3.33 ms which requires a 10 nF
capacitor.
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OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION
For the example design, 10.0 kΩ was selected for R6. Using Equation 16, R7 is calculated as 8.15 kΩ. A close
standard 1% resistor is 8.06 kΩ.
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The TPS5432 can regulate to output voltages at or above the internal voltage reference of 0.808 V. Theoretically,
the output voltage may be limited by the minimum controllable on time of the device. For the TPS5432, this
should never be an issue as the minimum output voltage of 0.808 V, maximum input voltage of 6 V and the fixed
operating frequency of 700 kHz will always result in on times above the minimum.
There is also a maximum achievable output voltage which is limited by the minimum off time of 60 nsec typical .
For normal operation, that limits the effective duty cycle to 95.8%. The TPS5432 can operate at higher effective
duty cycles. In this operating mode, the device will have some switching cycles where the on time is 100% of the
cycle. If the output current is increased further at this point, two discreet operating mode will occur sequentially.
In the first mode, the device will switch at the normal 700 kHz frequency with the off time at the minimum (60
nsec typical). in the second mode the every alternating switching cycle will be at 100 % on time followed by a
cycle with an off time greater than the minimum. The apparent effect is reduction of the operating frequency by
50%. The long term average duty cycle is greater than 95.8%, allowing the device to regulate with input voltages
that approach the output voltage.
COMPENSATION
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0
degrees at low frequencies and starts to fall one decade below the modulator pole frequency reaching a
minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole
shown in Equation 17.
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