Datasheet

TPS54329

www.ti.com

SLVSAZ6A –SEPTEMBER 2011–REVISED MARCH 2012

LAYOUT CONSIDERATIONS

1. Keep the input switching current loop as small as possible.

2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and

inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the

feedback pin of the device.

3. Keep analog and non-switching components away from switching components.

4. Make a single point connection from the signal ground to power ground.

5. Do not allow switching current to flow under the device.

6. Keep the pattern lines for VIN and PGND broad.

7. Exposed pad of device must be connected to PGND with solder.

8. VREG5 capacitor should be placed near the device, and connected PGND.

9. Output capacitor should be connected to a broad pattern of the PGND.

10. Voltage feedback loop should be as short as possible, and preferably with ground shield.

11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to analog ground

trace.

12. Providing sufficient vias for VIN, SW and PGND connection.

13. VIN input bypass capacitor and VIN high frequency bypass capacitor must be placed as near as possible to

the device.

14. Performance based on four layer printed circuit board.

Product Folder Link(s): TPS54329