Datasheet

SW
VBST
EN
VFB
GND
VO
4
5
6
2
1
7
VIN
SS
VIN
VREG5
EN
Logic
SW
PGND
Protection
Logic
Ref
SS
UVLO
UVLO
Softstart
SS
REF
TSD
Ref
VREG5
8
VIN
Ceramic
Capacitor
3
SGND
SGND
PGND
PWM
+
-
+
OCP
+
-
VREG5
XCON
VREG5
Control Logic
1 shot
ON
SW
PGND
ZC
+
-
TPS54328
www.ti.com SLVSAN2C –NOVEMBER 2010–REVISED NOVEMBER 2012
PIN FUNCTIONS
PIN
DESCRIPTION
NAME DDA DRC
EN 1 1 Enable input control. Active high.
VFB 2 2 Converter feedback input. Connect to output voltage with feedback resistor divider.
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND.
VREG5 3 3
VREG5 is not active when EN is low.
SS 4 4 Soft-start control. An external capacitor should be connected to GND.
Ground pin. Power ground return for switching circuit. Connect sensitive SS and
GND 5
VFB returns to GND at a single point.
GND 5 Ground pin. Connect sensitive SS and VFB returns to GND at a single point.
SW 6 6, 7 Switch node connection between high-side NFET and low-side NFET.
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor
VBST 7 8 between VBST and SW pins. An internal diode is connected between VREG5 and
VBST.
VIN 8 9, 10 Input voltage supply pin.
Exposed Thermal Thermal pad of the package. Must be soldered to achieve appropriate dissipation.
Back side
Pad Must be connected to GND.
Exposed Thermal Thermal pad of the package. PGND power ground return of internal low-side FET.
Back side
Pad Must be soldered to achieve appropriate dissipation.
FUNCTIONAL BLOCK DIAGRAM
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