Datasheet

TPS54328
SLVSAN2C –NOVEMBER 2010–REVISED NOVEMBER 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
TRANSPORT
T
A
PACKAGE
(2) (3)
ORDERABLE PART NUMBER PIN
MEDIA
TPS54328DDA Tube
DDA 8
TPS54328DDAR Tape and Reel
–40°C to 85°C
TPS54328DRCT Tape and Reel
DRC 10
TPS54328DRCR Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
MIN MAX
VIN, EN –0.3 20
VBST –0.3 26
VBST (10 ns transient) –0.3 28
Input voltage range VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5
SW –2 20
SW (10 ns transient) –3 22
VREG5 –0.3 6.5
Output voltage
V
range
GND –0.3 0.3
Voltage from GND to thermal pad, V
diff
–0.2 0.2 V
Human Body Model (HBM) 2 kV
Electrostatic
discharge
Charged Device Model (CDM) 500 V
Operating junction temperature, T
J
–40 150
°C
Storage temperature, T
stg
–55 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS54328
THERMAL METRIC
(1)
UNITS
DDA (8 PINS) DRC (10 PINS)
θ
JA
Junction-to-ambient thermal resistance 42.1 43.9
θ
JCtop
Junction-to-case (top) thermal resistance 50.9 55.4
θ
JB
Junction-to-board thermal resistance 31.8 18.9
°C/W
ψ
JT
Junction-to-top characterization parameter 5 0.7
ψ
JB
Junction-to-board characterization parameter 13.5 19.1
θ
JCbot
Junction-to-case (bottom) thermal resistance 7.1 5.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2 Copyright © 2010–2012, Texas Instruments Incorporated
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