Datasheet

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Tss(ms)=

C6(nF) Vref•

Iss( A)µ

−

C6(nF) • 0.765

−

TPS54325

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SLVS932D –MAY 2009–REVISED AUGUST 2012

OVERVIEW

The TPS54325 is a 3-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It

operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output

capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low

ESR output capacitors including ceramic and special polymer types.

DETAILED DESCRIPTION

PWM Operation

The main control loop of the TPS54325 is an adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with

an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one

shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to

maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The

one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the

reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the

need for ESR induced output ripple from D-CAP2™ mode control.

PWM Frequency and Adaptive On-Time Control

TPS54325 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The

TPS54325 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to

set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the

output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

Soft Start and Pre-Biased Soft Start

The TPS54325 has an adjustable soft start . When the EN pin becomes high, 2.0-μA current begins charging the

capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during

start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source

current is 2 μA.

(1)

The TPS54325 contains a unique circuit to prevent current from being pulled from the output during startup in the

condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level

(internal soft start becomes greater than feedback voltage (V

), the controller slowly activates synchronous

rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-

time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the

converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO)

starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-

up to normal mode operation.

Power Good

The TPS54325 has power-good output. The power-good function is activated after soft start has finished. If the

output voltage becomes within -10% of the target value, internal comparators detect power good state and the

power good signal becomes high. R

resister value ,which is connected between PG and VREG5, is required

from 20 kΩ to 150 kΩ. If the feedback voltage goes under 15% of the target value, the power good signal

becomes low after 10 μs internal delay.

Product Folder Links: TPS54325