Datasheet

VO
VFB
VREG5
SS
GND
PG
EN
VCC
VIN
VBST
SW2
SW1
PGND2
PGND1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
POWERPAD
TPS54325
PWP
HTSSOP14
PWP PACKAGE
(TOP VIEW)
TPS54325
www.ti.com SLVS932D –MAY 2009–REVISED AUGUST 2012
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME NO.
VO 1 Connect to output of converter. This terminal is used for On-Time Adjustment.
VFB 2 Converter feedback input. Connect with feedback resistor divider.
VREG5 3 5.5 V power supply output. A capacitor (typical 1μF) should be connected to GND.
SS 4 Soft-start control. A external capacitor should be connected to GND.
GND 5 Signal ground pin
PG 6 Open drain power good output
EN 7 Enable control input
Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and
PGND1, PGND2 8, 9
GND strongly together near the IC.
Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current
SW1, SW2 10, 11
comparators.
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to
VBST 12
respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
VIN 13 Power input and connected to high side NFET drain
VCC 14 Supply input for 5 V internal linear regulator for the control circuitry
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected
PowerPAD™ Back side
to PGND.
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