Datasheet

TPS54320
SLVS982A –AUGUST 2010–REVISED SEPTEMBER 2010 www.ti.com
The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for
the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor
voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to
recharge the boot capacitor. The device can operate at 100% duty cycle, as long as the boot capacitor voltage is
higher than the preset BOOT-PH UVLO threshold, which is typically 2.1V. The output voltage can be stepped
down to as low as the 0.8V voltage reference (Vref).
The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through
the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage
is less than 91% or greater than 109% of the reference voltage Vref and floats high when the VSENSE pin
voltage is 94% to 106% of the Vref.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor or resistor divider should be attached to the pin for slow start or critical
power supply sequencing requirements.
The device is protected from output overvoltage, overload and thermal fault conditions. The device minimizes
excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.
When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning
on until the VSENSE pin voltage is lower than 106% of the Vref. The device implements both high-side MOSFET
overload protection and bidirectional low-side MOSFET overload protections which help control the inductor
current and avoid current runaway. If the overcurrent condition has lasted for more than the hiccup wait time, the
device will shut down and restart after the hiccup time. The device also shuts down if the junction temperature is
higher than thermal shutdown trip point. The device is restarted under control of the slow start circuit
automatically when the junction temperature drops 10°C typically below the thermal shutdown trip point.
DETAILED DESCRIPTION
Fixed Frequency PWM Control
The device uses adjustable, fixed frequency, peak current mode control. The output voltage is compared through
external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the
COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is
converted into a current reference which is compared to the high-side power switch current. When the power
switch current reaches the current reference generated by the COMP voltage level, the high-side power switch is
turned off and the low-side power switch is turned on.
Continuous Current Mode Operation (CCM)
As a synchronous buck converter, the device normally works in CCM (Continuous Conduction Mode) under all
load conditions.
VIN and Power VIN Pins (VIN and PVIN)
The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN
pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to
the power converter system.
If tied together, the input voltage for VIN and PVIN can range from 4.5V to 17V. If using the VIN separately from
PVIN, the VIN pin must be between 4.5V and 17V, and the PVIN pin can range from as low as 1.6V to 17V. A
voltage divider connected to the EN pin can adjust either input voltage UVLO appropriately. Adjusting the input
voltage UVLO on the PVIN pin helps to provide consistent power up behavior.
Voltage Reference
The voltage reference system produces a precise voltage reference by scaling the output of a temperature stable
bandgap circuit.
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