Datasheet

( ) ( )
( )
Tss ms Iss A
C7(nF)
Vref V
×
=
m
Vout Vref
R8 R9
Vref
-
=
TPS54320
SLVS982A –AUGUST 2010–REVISED SEPTEMBER 2010 www.ti.com
Slow Start Capacitor Selection
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and requires a large amount of current to charge the capacitor to
the output voltage level. The large currents necessary to charge the capacitor may either make the TPS54320
reach the current limit or the excessive current draw from the input power supply may cause the input voltage rail
to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor value can be
calculated using Equation 29. The example circuit has the soft start time set to an arbitrary value of 3.5ms which
requires a 10nF capacitor. In the TPS54320, Iss is 2.3µA and Vref is 0.8V.
(29)
Bootstrap Capacitor Selection
A 0.1µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or
higher voltage rating.
Under Voltage Lockout Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R1 and R2.
R1 is connected between VIN and the EN pin of the TPS54320 and R2 is connected between EN and GND. The
UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brownouts when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.806V (UVLO start or enable). After the regulator starts
switching, it should continue to do so until the input voltage falls below 4.824V (UVLO stop or disable).
Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the
stop voltages specified, the nearest standard resistor value for R1 is 511 kΩ and for R2 is 100kΩ.
Output Voltage Feedback Resistor Selection
The resistor divider network, R8 and R9, is used to set the output voltage. For this example design, 10 kΩ was
selected for R9. Using Equation 30, R8 is calculated as 31.25kΩ. The nearest standard 1% resistor is 31.6kΩ.
(30)
Minimum Output Voltage
Due to the internal design of the TPS54320, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.8V. Above 0.8V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 31.
V
OUT
min = Ontimemin x Fsmax (V
IN
max + I
OUT
min (RDS2min - RDS1min)) - I
OUT
min (R
L
+ RDS2min) (31)
Where:
V
OUT
min = minimum achievable output voltage
Ontimemin = minimum controllable on time (135 nsec maximum)
Fsmax = maximum switching frequency including tolerance
V
IN
max = maximum input voltage
I
OUT
min = minimum load current
RDS1min = minimum high side MOSFET on resistance (57mΩ typical)
RDS2min = minimum low side MOSFET on resistance (50mΩ typical)
R
L
= series resistance of output inductor
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