Datasheet
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P -PowerDissipated-W
D
T -Maximum AmbientTemperature-°C
Amax
T =150°C,noairflow
Jmax
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T -JunctionTemperature-°C
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TPS54318
SLVS975A –SEPTEMBER 2009–REVISED SEPTEMBER 2013
www.ti.com
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator. As an example, the maximum ambient temperature
versus power dissipation for the EVM is shown in Figure 52.
Figure 51. Junction Temperature vs IC Power Dissipation
Figure 52. Maximum Ambient Temperature vs IC power Dissipation
LAYOUT
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the
bypass capacitor connections and the VIN pins. See Figure 53 for a PCB layout example. The GND pins and
AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any
internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the
top side ground area to the internal planes near the input and output capacitors. For operation at full rated load,
the top side ground area along with any additional internal ground planes must provide adequate heat dissipating
area.
Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output
inductor. Because the PH connection is the switching node, the output inductor should be located close to the
PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot
capacitor must also be located close to the device. The sensitive analog ground connections for the feedback
voltage divider, compensation components, slow-start capacitor and frequency set resistor should be connected
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