Datasheet

OUT
OUT OUT
I max
p mod =
2 V C
¦
p ´ ´
( )
( )
( )
( )
( )
( )
OUT S IN OUT DS OUT L DS
V max 1 Offtimemax F max V min I max 2 R I max R R= - ´ ´ - ´ ´ - ´ +
( )
( )
( )
(
)
( )
( )
OUT S IN OUT OUT L DS
V min Ontimemin F max V max I min 2 RDS I min R R= ´ ´ - ´ ´ - ´ +
ref
OUT ref
V
R7 = R6
V V-
TPS54318
www.ti.com SLVS975A –SEPTEMBER 2009–REVISED SEPTEMBER 2013
OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION
For the example design, 100 kΩ was selected for R6. Using Equation 31, R7 is calculated as 80 kΩ. The nearest
standard 1% resistor is 80.5 kΩ.
(31)
Due to the internal design of the TPS54318, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 32
where
• V
OUT
min = minimum achievable output voltage
• Ontimemin = minimum controllable on-time (60 ns typical. 110-ns no load)
• F
s
max = maximum switching frequency including tolerance
• V
IN
max = maximum input voltage
• I
OUT
min = minimum load current
• R
DS
= minimum high side MOSFET on resistance (30 - 44 mΩ)
• R
L
= series resistance of output inductor (32)
There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum
output voltage is given by Equation 33
where
• V
OUT
max = maximum achievable output voltage
• Offtimeman = maximum off time (60 ns typical)
• F
s
max = maximum switching frequency including tolerance
• V
IN
min = minimum input voltage
• I
OUT
max = maximum load current
• R
DS
= maximum high-side MOSFET on resistance (60 - 70 mΩ)
• R
L
= series resistance of output inductor (33)
COMPENSATION
There are several industry techniques used to compensate DC-DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54318. Because the slope compensation is ignored, the actual crossover frequency is usually lower than
the crossover frequency used in the calculations. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 34 and
Equation 12. For C
OUT
, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V
capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer
information to derate the capacitor value. Use Equation 36 and Equation 37 to estimate a starting point for the
crossover frequency, fc. For the example design, fpmod is 4.02 kHz and fzmod is 804 kHz. Equation 36 is the
geometric mean of the modulator pole and the ESR zero and Equation 37 is the mean of modulator pole and the
switching frequency. Equation 36 yields 5.6 kHz and Equation 37 gives 44.8 kHz. Use the lower value of
Equation 36 or Equation 37 as the maximum crossover frequency. For this example, fc is 45 kHz. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole (if needed).
(34)
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