Datasheet

-
×
- + × ´
6
STOP
1.18 R1
R2 =
V 1.18 R1 3.2 10
-
× -
´
START STOP
6
0.944 V V
R1 =
2.59 10
SS SS
SS
ref
T (mS) I ( A)
C (nF) =
V (V)
´ m
TPS54318
SLVS975A –SEPTEMBER 2009–REVISED SEPTEMBER 2013 www.ti.com
COMP VOLTAGE LEVEL
The TPS54318 implements a minimum COMP voltage clamp for improved load transient response. The COMP
voltage tracks the peak inductor current, increasing as the peak inductor current increases, and decreasing as
the peak inductor current decreases. During a severe load dump event, for instance, the COMP voltage
decreases suddenly, falls below the minimum clamp value, then settles to a lower DC value as the control loop
compensates for the transient event. During the time when COMP reaches the minimum clamp voltage, turn-on
of the high-side power switch is inhibited, keeping the low-side power switch on to discharge the output voltage
overshoot more quickly.
Proper application circuit design should ensure that the minimum load steady-state COMP voltage is above the
+3 sigma minimum clamp to avoid unwanted inhibition of the high side power switch. For a given design, the
steady-state DC level of COMP is measured at the minimum designed load, and the maximum designed input
voltage, then compared to the minimum COMP clamp voltage shown in Figure 22. These conditions represent
the minimum COMP voltage conditions for a given design. Generally, the COMP voltage and minimum clamp
voltage move about by the same amount with temperature. Increasing the minimum load COMP voltage is
accomplished by decreasing the the output inductor value or the switching frequency used in a given design.
SLOW START CAPACITOR
The slow-start capacitor determines the minimum amount of time for the output voltage to reach the nominal
programmed value during power up. The slow-start function is useful if a load requires a controlled voltage slew
rate. This function is also used if the output capacitance is large and would require large amounts of current to
quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor
cause the TPS54318 to reach the current limit, or excessive current draw from the input power supply can cause
the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow-start capacitor value is calculated using Equation 28. For the example circuit, the slow-start time is not
too critical because the output capacitor value is 44 μF which does not require much current to charge to 1.8 V.
The example circuit has the slow-start time set to an arbitrary value of 4 ms which requires a 10 nF capacitor. In
TPS54318, Iss is 2 μA and V
ref
is 0.8 V. TI Recommends keeping the soft-start time in the range of 1 ms to 10
ms.
(28)
BOOTSTRAP CAPACITOR SELECTION
A 0.1-μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. TI
recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or
higher voltage rating.
UNDERVOLTAGE LOCKOUT SET POINT
The Undervoltage Lockout (UVLO) is adjusted using an external voltage divider on the EN pin of the TPS54318.
The UVLO has two thresholds, one for power-up when the input voltage is rising and one for power-down or
brown-outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 3.1 V (V
START
). After the regulator starts switching, it should
continue to do so until the input voltage falls below 2.8 V (V
STOP
).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 29 and Equation 30 are used to calculate the resistance values necessary. From Equation 29 and
Equation 30, a 48.7 kΩ between Vin and EN and a 32.4 kΩ between EN and ground are required to produce the
3.1- and 2.8-V start and stop voltages.
(29)
(30)
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