Datasheet
TPS54317
www.ti.com
..................................................................................................................................... SLVS619B –NOVEMBER 2005–REVISED SEPTEMBER 2009
PACKAGE DISSIPATION RATINGS
(1) (2)
PACKAGE THERMAL IMPEDANCE THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT JUNCTION-TO-CASE
24-Pin RHF with solder 19.7°C/W 1.7°C/W
(1) Maximum power dissipation may be limited by overcurrent protection.
(2) Test board conditions:
(a) 3 inch x 3 inch, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground plane on the bottom of the PCB
(d) 2 oz. copper ground planes on the 2 internal layers
(e) 6 thermal vias (see the Recommended land pattern, Figure 12 )
ELECTRICAL CHARACTERISTICS
T
J
= –40°C to 125°C, V
I
= 3 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
V
I
Input voltage range, VIN 3 6 V
f
s
= 350 kHz, SYNC = 0.8 V, RT open 6.2 9.6
f
s
= 550 kHz, SYNC ≥ 2.5 V, RT open,
Quiescent current 8.4 12.8 mA
phase pin open
Shutdown, SS/ENA = 0 V 1 1.4
UNDERVOLTAGE LOCK OUT
Start threshold voltage, UVLO 2.95 3
V
Stop threshold voltage, UVLO 2.7 2.8
Hysteresis voltage, UVLO 0.14 0.16 V
Rising and falling edge deglitch,
2.5 µs
UVLO
(1)
BIAS VOLTAGE
Output voltage, VBIAS I
(VBIAS)
= 0 2.7 2.8 2.9 V
V
O
Output current, VBIAS
(2)
100 µA
CUMULATIVE REFERENCE
V
ref
Accuracy 0.882 0.891 0.900 V
REGULATION
Line regulation
(1) (3)
I
L
= 1.5 A, f
s
= 1.1 MHz, T
J
= 25°C 0.04 %/V
Load regulation
(1) (3)
I
L
= 0 A to 3 A, f
s
= 1.1 MHz, T
J
= 25°C 0.09 %/A
OSCILLATOR
SYNC ≤ 0.8 V, RT open 280 350 420
Internally set free-running frequency
kHz
range
SYNC ≥ 2.5 V, RT open 440 550 660
RT = 100 kΩ (1% resistor to AGND) 460 500 540
Externally set free-running frequency
kHz
range
RT = 43 kΩ (1% resistor to AGND) 995 1075 1155
High-level threshold voltage, SYNC 2.5 V
Low-level threshold voltage, SYNC 0.8 V
Pulse duration, SYNC
(1)
50 ns
Frequency range, SYNC 330 1600 kHz
Ramp valley
(1)
0.75 V
Ramp amplitude (peak-to-peak)
(1)
1 V
Minimum controllable on time 150 ns
Maximum duty cycle 90%
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10 .
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS54317