Datasheet

V max=0.9xV min-I max[(-0.016xV min+0.184)+RL]
O I O I
V min=(150E-9xV maxxFsx1.08)-I minx
O I o
X
V max
i
+0.111+RL
(
[ ]
)
-0.026
3
TPS54317
SLVS619B –NOVEMBER 2005–REVISED SEPTEMBER 2009 ..................................................................................................................................... www.ti.com
Thermal Shutdown
(5)
The device uses the thermal shutdown to turn off the
Where:
power MOSFETs and disable the controller if the
junction temperature exceeds 150°C. The device is
V
I
min = minimum input voltage
released from shutdown when the junction
I
O
max = maximum load current
temperature decreases to 10°C below the thermal
RL = series resistance of the output inductor
shutdown trip point and starts up under control of the
slow-start circuit. Thermal shutdown provides
Equation 5 assumes maximum on resistance for the
protection when an overload condition is sustained for
internal high-side and low-side FETs.
several milliseconds. With a persistent fault condition,
The lower limit is constrained by the minimum
the device cycles continuously; starting up by control
controllable on time which may be as high as 150 ns.
of the soft-start circuit, heating up due to the fault,
The approximate minimum output voltage for a given
and then shutting down upon reaching the thermal
input voltage, operating frequency, and minimum load
shutdown point.
current is given in Equation 6:
Power Good (PWRGD)
The power good circuit monitors for undervoltage
conditions on VSENSE. If the voltage on VSENSE is
(6)
10% below the reference voltage, the open-drain
PWRGD output is pulled low. PWRGD is also pulled
Where:
low if VIN is less than the UVLO threshold, or
V
I
= maximum input voltage
SS/ENA is low, or thermal shutdown is asserted.
Fs = programmed operating frequency
When VIN = UVLO threshold, SS/ENA = enable
threshold, and VSENSE > 90% of V
ref
, the open drain
I
O
= minimum load current
output of the PWRGD pin is high. A hysteresis
RL = series resistance of the output inductor
voltage equal to 3% of V
ref
and a 35-μs falling edge
Equation 6 assumes nominal on resistance for the
deglitch circuit prevent tripping of the power good
high-side and low-side FETs, and has an eight
comparator due to high frequency noise.
percent factor for variation of operating frequency set
point. Any design operating near the operational limits
OUTPUT VOLTAGE LIMITATIONS
of the device should be carefully checked for proper
Due to the internal design of the TPS54317, there are
functionality.
both upper and lower output voltage limits for any
given input voltage. Additionally, the lower boundary
of the output voltage set point range is also
dependent on operating frequency. The upper limit of
the output voltage set point is constrained by the
maximum duty cycle of 90% and is given by
Equation 5:
REVISION HISTORY
Changes from Original (November 2005) to Revision A ................................................................................................ Page
• Changed Abs Max Table - From: V
O
- PH (transient) value -1.5 to 10 V To: PH (transient < 20 ns) value -2 to 10 V ........ 2
• Added MAX value = 3V to the Electrical Characteristics - Start threshold voltage, UVLO .................................................. 3
• Changed the Functional Block Diagram component value near pin BOOT From: 30 mΩ To: 59 mΩ ................................. 6
• Changed Figure 1 label From: Drain-Source On-State Resistabce - Ω To: Drain-Source On-State Resistabce - mΩ ....... 7
• Changed Figure 2 label From: Drain-Source On-State Resistabce - Ω To: Drain-Source On-State Resistabce - mΩ ....... 7
Changes from Revision A (February 2006) to Revision B ............................................................................................. Page
• Added Voltage to regulate using the internal V
ref
, SS/ENA .................................................................................................. 4
• Added text to the first paragraph of the Slow-Start/Enable (SS/ENA) section - To make sure the part is regulating
using the internal Vref, the SS/ENA pin must be pulled above 1.95 V typically, 2.2 V max. ............................................. 12
14 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS54317