Datasheet

TPS54317
www.ti.com ..................................................................................................................................... SLVS619B –NOVEMBER 2005–REVISED SEPTEMBER 2009
Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY SYNC PIN RT PIN
350 kHz, internally set Float or AGND Float
550 kHz, internally set ≥ 2.5 V Float
Externally set 280 kHz to 1600 kHz Float R = 27.4 k to 180 k
Externally synchronized frequency Synchronization signal R = RT value for 80% of external synchronization frequency
Error Amplifier
The high performance, wide bandwidth, voltage error low-side FET remains on until the VSENSE voltage
amplifier sets the TPS54317 apart from most dc/dc decreases to a range that allows the PWM
converters. The user is given the flexibility to use a comparator to change states. The TPS54317 is
wide range of output L and C filter components to suit capable of sinking current continuously until the C
O
the particular application needs. Type 2 or type 3 reaches the regulation set-point.
compensation can be employed using external
If the current limit comparator trips for longer than
compensation components.
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side FET
PWM Control
turns off and low-side FET turns on to decrease the
Signals from the error amplifier output, oscillator, and energy in the output inductor, and consequently, the
current limit circuit are processed by the PWM control output current. This process is repeated each cycle in
logic. Referring to the internal block diagram, the which the current limit comparator is tripped.
control logic includes the PWM comparator, OR gate,
PWM latch, and portions of the adaptive dead-time Dead-Time Control and MOSFET Drivers
and control logic block. During steady-state operation
Adaptive dead-time control prevents shoot-through
below the current limit threshold, the PWM
current from flowing in both N-channel power
comparator output and oscillator pulse train
MOSFETs during the switching transitions by actively
alternately reset and set the PWM latch. Once the
controlling the turn-on times of the MOSFET drivers.
PWM latch is set, the low-side FET remains on for a
The high-side driver does not turn on until the gate
minimum duration set by the oscillator pulse duration.
drive voltage to the low-side FET is below 2 V. The
During this period, the PWM ramp discharges rapidly
low-side driver does not turn on until the voltage at
to its valley voltage. When the ramp begins to charge
the gate of the high-side MOSFETs is below 2 V. The
back up, the low-side FET turns off and high-side
high-side and low-side drivers are designed with a
FET turns on. As the PWM ramp voltage exceeds the
300-mA source and sink capability to drive the power
error amplifier output voltage, the PWM comparator
MOSFETs gates. The low-side driver is supplied from
resets the latch, thus turning off the high-side FET
VIN, while the high-side drive is supplied from the
and turning on the low-side FET. The low-side FET
BOOT pin. A bootstrap circuit uses an external BOOT
remains on until the next oscillator pulse discharges
capacitor and an internal 2.5-Ω bootstrap switch
the PWM ramp.
connected between the VIN and BOOT pins. The
During transient conditions, the error amplifier output integrated bootstrap switch improves drive efficiency
could be below the PWM ramp valley voltage or and reduces external component count.
above the PWM peak voltage. If the error amplifier is
high, the PWM latch is never reset and the high-side Overcurrent Protection
FET remains on until the oscillator pulse signals the
The cycle by cycle current limiting is achieved by
control logic to turn off the high-side FET and turns
sensing the current flowing through the high-side
on the low-side FET. The device operates at its
MOSFET and differential amplifier, and comparing it
maximum duty cycle until the output voltage rises to
to the preset overcurrent threshold. The high-side
the regulation set-point, setting VSENSE to
MOSFET is turned off within 200 ns of reaching the
approximately the same voltage as V
ref
. If the error
current limit threshold. A 100-ns leading edge
amplifier output is low, the pwm latch is continually
blanking circuit prevents false tripping of the current
reset and the high-side FET does not turn on. The
limit. Current limit detection occurs only when current
flows from VIN to PH when sourcing current to the
output filter. Load protection during current sink
operation is provided by thermal shutdown.
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