Datasheet

t
(SS)
+ C
(SS)
0.7 V
5 mA
t
d
+ C
(SS)
1.2 V
5 mA
SWITCHINGFREQUENCY (MHz)=
51k
R( )+4.7kW
TPS54317
SLVS619B –NOVEMBER 2005–REVISED SEPTEMBER 2009 ..................................................................................................................................... www.ti.com
DETAILED DESCRIPTION
(3)
Undervoltage Lock Out (UVLO)
The actual slow-start is likely to be less than the
The TPS54317 incorporates an undervoltage lockout
above approximation due to the brief ramp-up at the
circuit to keep the device disabled when the input
internal rate.
voltage (VIN) is insufficient. During power up, internal
circuits are held inactive until VIN exceeds the
VBIAS Regulator (VBIAS)
nominal UVLO threshold voltage of 2.95 V. Once the
The VBIAS regulator provides internal analog and
UVLO start threshold is reached, device start-up
digital blocks with a stable supply voltage over
begins. The device operates until VIN falls below the
variations in junction temperature and input voltage. A
nominal UVLO stop threshold of 2.8 V. Hysteresis in
high quality, low-ESR, ceramic bypass capacitor is
the UVLO comparator, and a 2.5-µs rising and falling
required on the VBIAS pin. X7R or X5R grade
edge deglitch circuit reduce the likelihood of shutting
dielectrics are recommended because their values
the device down due to noise on VIN.
are more stable over temperature. The bypass
capacitor should be placed close to the VBIAS pin
Slow-Start/Enable (SS/ENA)
and returned to AGND. External loading on VBIAS is
The slow-start/enable pin provides two functions; first,
allowed, with the caution that internal circuits require
the pin acts as an enable (shutdown) control by
a minimum VBIAS of 2.70 V, and external loads on
keeping the device turned off until the voltage
VBIAS with ac or digital switching noise may degrade
exceeds the start threshold voltage of approximately
performance. The VBIAS pin may be useful as a
1.2 V. When SS/ENA exceeds the enable threshold,
reference voltage for external circuits.
device start up begins. The reference voltage fed to
the error amplifier is linearly ramped up from 0 V to
Voltage Reference
0.891 V in 3.35 ms. To make sure the part is
The voltage reference system produces a precise V
ref
regulating using the internal V
ref
, the SS/ENA pin
signal by scaling the output of a temperature stable
must be pulled above 1.95 V typically, 2.2 V max.
bandgap circuit. During manufacture, the bandgap
Similarly, the converter output voltage reaches
and scaling circuits are trimmed to produce 0.891 V
regulation in approximately 3.35 ms. Voltage
at the output of the error amplifier, with the amplifier
hysteresis and a 2.5-μs falling edge deglitch circuit
connected as a voltage follower. The trim procedure
reduce the likelihood of triggering the enable due to
adds to the high precision regulation of the
noise.
TPS54317, since it cancels offset errors in the scale
The second function of the SS/ENA pin provides an
and error amplifier circuits.
external means of extending the slow-start time with
a low-value capacitor connected between SS/ENA
Oscillator and PWM Ramp
and AGND. Adding a capacitor to the SS/ENA pin
The oscillator frequency can be set to internally fixed
has two effects on start-up. First, a delay occurs
values of 350 kHz or 550 kHz using the SYNC pin as
between release of the SS/ENA pin and start up of
a static digital input. If a different frequency of
the output. The delay is proportional to the slow-start
operation is required for the application, the oscillator
capacitor value and lasts until the SS/ENA pin
frequency can be externally adjusted from 280 kHz to
reaches the enable threshold. The start-up delay is
1600 kHz by connecting a resistor to the RT pin to
approximately:
ground and floating the SYNC pin. The switching
frequency is approximated by the following equation,
(2)
where R is the resistance from RT to AGND:
Second, as the output becomes active, a brief
ramp-up at the internal slow-start rate may be (4)
observed before the externally set slow-start rate
External synchronization of the PWM ramp is
takes control and the output rises at a rate
possible over the frequency range of 330 kHz to 1600
proportional to the slow-start capacitor. The slow-start
kHz by driving a synchronization signal into SYNC
time set by the capacitor is approximately:
and connecting a resistor from RT to AGND. Choose
an RT resistor that sets the free-running frequency to
80% of the synchronization signal. Table 1
summarizes the frequency selection configurations.
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