Datasheet

Layout
3-2
3.1 Layout
The top-side (component) layer for the TPS54314EVM is shown in
Figure 3–1. The input capacitor (C6), bias decoupling capacitor (C7), and
bootstrap capacitor (C5) are all located as close to the IC as possible.
The TPS54314EVM PWB consists of two layers of 1.5 oz. copper. The bottom
half of the top layer is used as a power ground plane, while the bottom layer
is used as a quiet (analog) ground plane. A wide power ground plane is used
to keep the power ground current from degrading the load regulation. The two
ground planes tie together at U1 to keep the ground current from injecting
noise between the analog and power grounds. A total of 10 vias are used to
tie the thermal land area under the TPS54314 device to the thermal plane on
the backside of the board.
Figure 3–1. Top Side Assembly