Datasheet

www.ti.com
OPERATING FREQUENCY
R +
100 kW
ƒ
SW
500 kHz
(2)
OUTPUT FILTER
PCB LAYOUT
TPS54310
SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007
this ground area to any internal ground planes. Use
additional vias at the ground side of the input and
output filter capacitors as well. The AGND and
In the application circuit, the 350-kHz operation is
PGND pins should be tied to the PCB ground by
selected by leaving RT and SYNC open. Connecting
connecting them to the ground area under the device
a 68-k Ω to 180-k Ω resistor between RT (pin 20) and
as shown. The only components that should tie
analog ground can be used to set the switching
directly to the power ground plane are the input
frequency from 280 kHz to 700 kHz. To calculate the
capacitors, the output capacitors, the input voltage
RT resistor, use the Equation 2 :
decoupling capacitor, and the PGND pins of the
TPS54310. Use a separate wide trace for the analog
ground signal path. This analog ground should be
used for the voltage set point divider, timing resistor
RT, slow start capacitor and bias capacitor grounds.
Connect this trace directly to AGND (pin 1).
The output filter is composed of a 1.2-µH inductor
The PH pins should be tied together and routed to
and 180-µF capacitor. The inductor is a low dc
the output inductor. Since the PH connection is the
resistance (0.017 Ω ) type, Coilcraft
switching node, inductor should be located very
DO1813P-122HC. The capacitor used is a 4-V
close to the PH pins and the area of the PCB
special polymer type with a maximum ESR of 0.015
conductor minimized to prevent excessive capacitive
Ω . The feedback loop is compensated so that the
coupling.
unity gain frequency is approximately 75 kHz.
Connect the boot capacitor between the phase node
and the BOOT pin as shown. Keep the boot
capacitor close to the IC and minimize the conductor
Figure 11 shows a generalized PCB layout guide for
trace lengths.
the TPS54310.
Connect the output filter capacitor(s) as shown
The VIN pins should be connected together on the
between the VOUT trace and PGND. It is important
printed circuit board (PCB) and bypassed with a low
to keep the loop formed by the PH pins, Lout, Cout
ESR ceramic bypass capacitor. Care should be
and PGND as small as practical.
taken to minimize the loop area formed by the
bypass capacitor connections, the VIN pins, and the
Place the compensation components from the VOUT
TPS54X10 ground pins. The minimum recommended
trace to the VSENSE and COMP pins. Do not place
bypass capacitance is 10-µF ceramic with a X5R or
these components too close to the PH trace. Due to
X7R dielectric and the optimum placement is closest
the size of the IC package and the device pinout,
to the VIN pins and the PGND pins.
they will have to be routed somewhat close, but
maintain as much separation as possible while still
The TPS54310 has two internal grounds (analog and
keeping the layout compact.
power). Inside the TPS54310, the analog ground ties
to all of the noise sensitive signals, while the power
Connect the bias capacitor from the VBIAS pin to
ground ties to the noisier power signals. Noise
analog ground using the isolated analog ground
injected between the two grounds can degrade the
trace. If a slow-start capacitor or RT resistor is used,
performance of the TPS54310, particularly at higher
or if the SYNC pin is used to select 350-kHz
output currents. Ground noise on an analog ground
operating frequency, connect them to this trace as
plane can also cause problems with some of the
well.
control and bias signals. For these reasons, separate
analog and power ground traces are recommended.
There should be an area of ground one the top layer
directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect
9
Submit Documentation Feedback