Datasheet
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APPLICATION INFORMATION
RT
SYNC
SS/ENA
VBIAS
PWRGD
COMP
VSENSE
AGND
20
19
18
17
4
3
2
1
VIN
VIN
VIN
PH
PH
PH
PH
PH
BOOT
PGND
PGND
PGND
PwrPAD
16
15
14
10
9
8
7
6
5
13
12
11
U1
TPS54310PWP
C8
10 µF
C7
0.047 µF
L1
1.2 µH
+
C9
180 µF
4 V
C11
1000 pF
1
2
V
O
GND
J3
C5
3900 pF
R2
3.74 kΩ
R4
3.74 kΩ
C4
100 pF
R3
71.5 kΩ
C3
0.1 µF
1
R1
10 kΩ
J1
2
1
V
I
GND
PWRGD
+
C2
1
Optional
C6
R6
2700 pF
732 Ω
R5
10 kΩ
R7
49.9 Ω
VIN
INPUT VOLTAGE SETTING THE OUTPUT VOLTAGE
FEEDBACK CIRCUIT
O
R5 x 0.891
R4 =
V - 0.891
(1)
TPS54310
SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007
Figure 10 shows the schematic diagram for a typical TPS54310 application. The TPS54310 (U1) can provide up
to 3 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the power pad
underneath the TPS54310 integrated circuit needs to be soldered well to the printed-circuit board.
Figure 10. TPS54310 Schematic
The input to the circuit is a nominal 5 VDC, applied The output voltage of the TPS54310 can be set by
at J1. The optional input filter (C2) is a 220-µF feeding back a portion of the output to the VSENSE
POSCAP capacitor, with a maximum allowable ripple pin using a resistor divider network. In the application
current of 3 A. C8 is the decoupling capacitor for the circuit of Figure 10 , this divider network is comprised
TPS54310 and must be located as close to the of resistors R5 and R4. To calculate the resistor
device as possible. values to generate the required output voltage use
Equation 1 .
The resistor divider network of R5 and R4 sets the
output voltage for the circuit at 3.3 V. R5, along with
Start with a fixed value of R5 and calculate the
R2, R6, C4, C5, and C6 forms the loop
required R4 value. Assuming a fixed value of 10 k Ω
compensation network for the circuit. For this design,
for R5, the following table gives the appropriate R4
a Type 3 topology is used.
value for several common output voltages:
OUTPUT VOLTAGE (V) R4 VALUE (K Ω )
1.2 28.7
1.5 14.7
1.8 9.76
2.5 5.49
3.3 3.74
8
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