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FEATURES DESCRIPTION

APPLICATIONS

Simplified Schematic

0 0.5 1 1.5 2 2.5 3

Load Current − A

Efficiency − %

= 25°C

= 5 V

= 3.3 V

EFFICIENCY

LOAD CURRENT

VIN PH

BOOT

PGND

VSENSE

Output

COMPAGND

VBIAS

Input

TPS54310

SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007

3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM

SWITCHER WITH INTEGRATED FETs (SWIFT™)

• 60-m Ω MOSFET Switches for High Efficiency

As members of the SWIFT™ family of dc/dc

at 3-A Continuous Output Source or Sink

regulators, the TPS54310 low-input-voltage high-

Current

output-current synchronous-buck PWM converter

integrates all required active components. Included

• Adjustable Output Voltage Down to 0.9 V With

on the substrate with the listed features are a true,

1% Accuracy

high performance, voltage error amplifier that

• Externally Compensated for Design Flexibility

provides high performance under transient

• Fast Transient Response

conditions; an undervoltage-lockout circuit to prevent

start-up until the input voltage reaches 3 V; an

• Wide PWM Frequency: Fixed 350 kHz, 550

internally and externally set slow-start circuit to limit

kHz, or Adjustable 280 kHz to 700 kHz

in-rush currents; and a power good output useful for

• Load Protected by Peak Current Limit and

processor/logic reset, fault signaling, and supply

Thermal Shutdown

sequencing.

• Integrated Solution Reduces Board Area and

The TPS54310 device is available in a thermally

Total Cost

enhanced 20-pin TSSOP (PWP) PowerPAD™

package, which eliminates bulky heatsinks. TI

provides evaluation modules and the SWIFT

designer software tool to aid in quickly achieving

• Low-Voltage, High-Density Systems With

high- performance power supply designs to meet

Power Distributed at 5 V or 3.3 V

aggressive equipment development cycles.

• Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs, and

Microprocessors

• Broadband, Networking and Optical

Communications Infrastructure

• Portable Computing/Notebook PCs

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

PAGE 1
www.ti.com TPS54310 SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT™) FEATURES • • • • • • • DESCRIPTION 60-mΩ MOSFET Switches for High Efficiency at 3-A Continuous Output Source or Sink Current Adjustable Output Voltage Down to 0.
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TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) TJ OUTPUT VOLTAGE PACKAGED DEVICES PLASTIC HTSSOP (PWP) (1) (2) –40°C to 125°C Adjustable Down to 0.
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TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 PACKAGE DISSIPATION RATINGS (1) (2) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 20-Pin PWP with solder 26°C/W 3.85 W (3) 2.12 W 1.54 W 20-Pin PWP without solder 57.5°C/W 1.73 W 0.96 W 0.69 W (1) (2) (3) For more information on the PWP package, refer to TI technical brief, literature number SLMA002. Test board conditions: 1.
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TPS54310 www.ti.
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TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 PIN ASSIGNMENTS PWP PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH 20 19 18 17 16 15 14 13 12 11 RT SYNC SS/ENA VBIAS VIN VIN VIN PGND PGND PGND TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Make PowerPAD connection to AGND. BOOT 5 Bootstrap input. 0.
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TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 FUNCTIONAL BLOCK DIAGRAM VBIAS AGND VIN Enable Comparator SS/ENA Falling Edge Deglitch 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator VIN 2.95 V Hysteresis: 0.16 V REG VBIAS SHUTDOWN VIN ILIM Comparator Thermal Shutdown 150°C 3−6V Leading Edge Blanking Falling and Rising Edge Deglitch 100 ns BOOT 30 mΩ 2.5 µs SS_DIS SHUTDOWN Internal/External Slow-start (Internal Slow-start Time = 3.
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TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE VI = 3.3 V 100 IO = 3 A 80 60 40 20 0 −40 0 25 85 VI = 5 V IO = 3 A 80 60 40 20 0 −40 125 f − Externally Set Oscillator Frequency − kHz TJ − Junction Temperature − °C 25 85 SYNC ≥ 2.5 V 550 450 SYNC ≤ 0.
PAGE 8
TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 APPLICATION INFORMATION Figure 10 shows the schematic diagram for a typical TPS54310 application. The TPS54310 (U1) can provide up to 3 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the power pad underneath the TPS54310 integrated circuit needs to be soldered well to the printed-circuit board. J1 VI GND VIN 2 1 C2 + R3 1 R1 10 kΩ 71.
PAGE 9
TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 OPERATING FREQUENCY In the application circuit, the 350-kHz operation is selected by leaving RT and SYNC open. Connecting a 68-kΩ to 180-kΩ resistor between RT (pin 20) and analog ground can be used to set the switching frequency from 280 kHz to 700 kHz. To calculate the RT resistor, use the Equation 2: R + 100 kW 500 kHz ƒ SW (2) OUTPUT FILTER The output filter is composed of a 1.2-µH inductor and 180-µF capacitor.
PAGE 10
TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 ANALOG GROUND TRACE FREQUENCY SET RESISTOR AGND RT COMPENSATION NETWORK COMP SS/ENA PWRGD BOOT CAPACITOR SLOW START CAPACITOR SYNC VSENSE VBIAS BIAS CAPACITOR EXPOSED POWERPAD AREA BOOT VIN PH VIN PH VIN PH PGND PH PGND PH PGND Vin VOUT OUTPUT INDUCTOR PH INPUT BYPASS CAPACITOR OUTPUT FILTER CAPACITOR INPUT BULK FILTER TOPSIDE GROUND AREA VIA to Ground Plane Figure 11.
PAGE 11
TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 PERFORMANCE GRAPHS EFFICIENCY vs OUTPUT CURRENT OUTPUT VOLTAGE vs LOAD CURRENT VI = 4 V VI = 6 V 85 80 75 70 Phase 40 90 3.36 3.34 Gain − dB VO − Output Voltage − % 3.32 3.3 45 20 Gain 0 0 TA = 25°C 3.28 −45 −20 3.26 0 1 2 3 4 −40 3.24 5 0 1 IO − Output Current − A 2 3 4 5 IL − Load Current − A 100 1k 10 k 100 k Figure 14. Figure 15.
PAGE 12
TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 VBIAS Regulator (VBIAS) DETAILED DESCRIPTION Under Voltage Lock Out (UVLO) The TPS54310 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins.
PAGE 13
TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 Table 1. Summary of the Frequency Selection Configurations SWITCHING FREQUENCY SYNC PIN RT PIN 350 kHz, internally set Float or AGND Float 550 kHz, internally set ≥ 2.
PAGE 14
TPS54310 www.ti.com SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007 Thermal Shutdown Power Good (PWRGD) The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to 10°C below the thermal shutdown trip point and starts up under control of the slow-start circuit.
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54310PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 20 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54310PWPR HTSSOP PWP 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.