Datasheet

OPERATING FREQUENCY
R +
100 kW
ƒ
SW
500 kHz
(2)
OUTPUT FILTER
PCB LAYOUT
TPS54310-EP
www.ti.com ..................................................................................................................................................................................................... SLVS818 – APRIL 2008
There should be an area of ground one the top layer
directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect
In the application circuit, the 350-kHz operation is
this ground area to any internal ground planes. Use
selected by leaving RT and SYNC open. Connecting
additional vias at the ground side of the input and
a 68-k Ω to 180-k Ω resistor between RT (pin 20) and
output filter capacitors as well. The AGND and PGND
analog ground can be used to set the switching
pins should be tied to the PCB ground by connecting
frequency from 280 kHz to 700 kHz. To calculate the
them to the ground area under the device as shown.
RT resistor, use the Equation 2 :
The only components that should tie directly to the
power ground plane are the input capacitors, the
output capacitors, the input voltage decoupling
capacitor, and the PGND pins of the TPS54310. Use
a separate wide trace for the analog ground signal
path. This analog ground should be used for the
The output filter is composed of a 1.2-µH inductor voltage set point divider, timing resistor RT, slow start
and 180-µF capacitor. The inductor is a low dc capacitor and bias capacitor grounds. Connect this
resistance (0.017 Ω ) type, Coilcraft DO1813P-122HC. trace directly to AGND (pin 1).
The capacitor used is a 4-V special polymer type with
The PH pins should be tied together and routed to
a maximum ESR of 0.015 Ω . The feedback loop is
the output inductor. Since the PH connection is the
compensated so that the unity gain frequency is
switching node, inductor should be located very close
approximately 75 kHz.
to the PH pins and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node
Figure 11 shows a generalized PCB layout guide for
and the BOOT pin as shown. Keep the boot capacitor
the TPS54310.
close to the IC and minimize the conductor trace
lengths.
The VIN pins should be connected together on the
printed circuit board (PCB) and bypassed with a low
Connect the output filter capacitor(s) as shown
ESR ceramic bypass capacitor. Care should be taken
between the VOUT trace and PGND. It is important to
to minimize the loop area formed by the bypass
keep the loop formed by the PH pins, Lout, Cout and
capacitor connections, the VIN pins, and the
PGND as small as practical.
TPS54X10 ground pins. The minimum recommended
bypass capacitance is 10-µF ceramic with a X5R or Place the compensation components from the VOUT
X7R dielectric and the optimum placement is closest trace to the VSENSE and COMP pins. Do not place
to the VIN pins and the PGND pins. these components too close to the PH trace. Due to
the size of the IC package and the device pinout,
The TPS54310 has two internal grounds (analog and
they will have to be routed somewhat close, but
power). Inside the TPS54310, the analog ground ties
maintain as much separation as possible while still
to all of the noise sensitive signals, while the power
keeping the layout compact.
ground ties to the noisier power signals. Noise
injected between the two grounds can degrade the Connect the bias capacitor from the VBIAS pin to
performance of the TPS54310, particularly at higher analog ground using the isolated analog ground
output currents. Ground noise on an analog ground trace. If a slow-start capacitor or RT resistor is used,
plane can also cause problems with some of the or if the SYNC pin is used to select 350-kHz
control and bias signals. For these reasons, separate operating frequency, connect them to this trace as
analog and power ground traces are recommended. well.
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Product Folder Link(s): TPS54310-EP