Datasheet

AGND
BOOT
VSENSE
COMP
PWRGD
PH
PH
PH
PH
PH
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
VOUT
PH
Vin
TOPSIDE GROUND AREA
VIA to Ground Plane
ANALOG GROUND TRACE
EXPOSED
POWERPAD
AREA
COMPENSATION
NETWORK
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
FREQUENCY SET RESISTOR
SLOW START
CAPACITOR
BIAS CAPACITOR
LAYOUT CONSIDERATIONS FOR THERMAL
TPS54310-EP
SLVS818 – APRIL 2008 ..................................................................................................................................................................................................... www.ti.com
Figure 11. TPS54310 PCB Layout
PERFORMANCE
For operation at full rated load current, the analog
ground plane must provide adequate heat dissipating
area. A 3 inch by 3 inch plane of 1 ounce copper is
recommended, though not mandatory, depending on
ambient temperature and airflow. Most applications
have larger areas of internal ground plane available,
and the PowerPAD should be connected to the
largest area available. Additional areas on the top or
bottom layers also help dissipate heat, and any area
available should be used when 3 A or greater
operation is desired. Connection from the exposed
area of the PowerPAD to the analog ground plane
layer should be made using 0.013 inch diameter vias
to avoid solder wicking through the vias. Six vias
should be in the PowerPAD area with four additional
vias located under the device package. The size of
the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018.
Additional vias beyond the ten recommended that
enhance thermal performance should be included in
areas not under the device package.
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Product Folder Link(s): TPS54310-EP